Arm: Completion of memory accesses not guaranteed by completion of a TLBI

ISSUE DESCRIPTION A hardware issue has been identified in certain Arm CPU designs. A broadcast TLBI on one PE may complete before affected memory accesses on another PE are globally observed. This may permit bypass of Stage 1 translation, Stage 2 translation, or GPT protection. The erratum occurs...

Linux Distros Unpatched Vulnerability : CVE-2024-5660

The Linux/Unix host has one or more packages installed that are impacted by a vulnerability without a vendor supplied patch available. - Use of Hardware Page Aggregation HPA and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1,...

SUSE CVE-2024-5660

Use of Hardware Page Aggregation HPA and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass o...

PT-2024-36907

Name of the Vulnerable Software and Affected Versions Arm Cortex processors versions A77 through X925, including A78, A78C, A78AE, A710, X1, X1C, X2, X3, X4, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 Description The use of Hardware Page Aggregation HPA and Stage-1 and/or...