CVE-2023-53043 arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent

In the Linux kernel, the following vulnerability has been resolved: arm64: dts: qcom: sc7280: Mark PCIe controller as cache coherent If the controller is not marked as cache coherent, then kernel will try to ensure coherency during dma-ops and that may cause data corruption. So, mark the PCIe nod...

CVE-2025-22012

In the Linux kernel, the following vulnerability has been resolved: Revert "arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on appssmmu" There are reports that the pagetable walker cache coherency is not a given across the spectrum of SDM845/850 devices, leading to lock-ups and resets. It works fine o...

UBUNTU-CVE-2025-22012

In the Linux kernel, the following vulnerability has been resolved: Revert "arm64: dts: qcom: sdm845: Affirm IDR0.CCTW on appssmmu" There are reports that the pagetable walker cache coherency is not a given across the spectrum of SDM845/850 devices, leading to lock-ups and resets. It works fine o...

CVE-2025-22012

The CVE-2025-22012 entry concerns the Linux kernel arm64/dts path: qcom/sdm845. The underlying issue relates to pagetable walker cache coherency, causing lock-ups and device-specific resets on SDM845/850 devices (e.g., Dragonboard 845c vs. Lenovo Yoga C630). The resolution described in the docume...

SUSE CVE-2005-3105

The mprotect code mprotect.c in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections...

CVE-2020-0550

A flaw was found in the Intel CPU's cache coherency mechanism. A microarchitectural hardware implementation issue that could allow an unprivileged local attacker to bypass conventional system security controls to infer on-CPU Level 1 cache contents is present. At this time, this specific flaw is...

security flaw

The mprotect code mprotect.c in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections...

CVE-2005-3105

The mprotect code mprotect.c in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections...

CVE-2005-3105

The mprotect code mprotect.c in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections...

CVE-2005-3105

CVE-2005-3105 affects the Linux kernel 2.6 on Itanium IA-64 Montecito (IA-64) where the mprotect code may lose cache coherency, enabling local users to cause a denial of service and possibly corrupt data by modifying PTE protections. Public advisories in connected documents (e.g., Debian DSA-922,...

CVE-2005-3105

The mprotect code mprotect.c in Linux 2.6 on Itanium IA64 Montecito processors does not properly maintain cache coherency as required by the architecture, which allows local users to cause a denial of service and possibly corrupt data by modifying PTE protections...