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Microarchitectural Data Sampling Advisory

Description

### Summary: A potential security vulnerability in CPUs may allow information disclosure. Intel is releasing Microcode Updates (MCU) updates to mitigate this potential vulnerability. ### Vulnerability Details: CVEID: [CVE-2018-12126](<http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-12126>) Microarchitectural Store Buffer Data Sampling (MSBDS): Store buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. CVSS Base Score: 6.5 Medium CVSS Vector: [CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N](<https://www.first.org/cvss/calculator/3.0#CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N>) CVEID: [CVE-2018-12127](<http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-12127>) Microarchitectural Load Port Data Sampling (MLPDS): Load ports on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. CVSS Base Score: 6.5 Medium CVSS Vector: [CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N](<https://www.first.org/cvss/calculator/3.0#CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N>) CVEID: [CVE-2018-12130](<http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-12130>) Microarchitectural Fill Buffer Data Sampling (MFBDS): Fill buffers on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. CVSS Base Score: 6.5 Medium CVSS Vector: [CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N](<https://www.first.org/cvss/calculator/3.0#CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:N/A:N>) CVEID: [CVE-2019-11091](<http://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2019-11091>) Microarchitectural Data Sampling Uncacheable Memory (MDSUM): Uncacheable memory on some microprocessors utilizing speculative execution may allow an authenticated user to potentially enable information disclosure via a side channel with local access. CVSS Base Score: 3.8 Low CVSS Vector: [CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:L/I:N/A:N](<https://www.first.org/cvss/calculator/3.0#CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:C/C:L/I:N/A:N>)__ ### Affected Products: A list of impacted products can be found [here.](<https://software.intel.com/security-software-guidance/processors-affected-transient-execution-attack-mitigation-product-cpu-model>) ### Recommendation: Intel has worked with operating system vendors, equipment manufacturers, and other ecosystem partners to develop platform firmware and software updates that can help protect systems from these methods. This includes the release of updated Intel microprocessor microcode to our customers and partners. Intel has released microcode updates for the affected Intel® Processors that are currently supported on the public github repository. Please see details below on access to the microcode: Public Github: <https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files> GitHub® link for 10th Generation Intel® Core™ Processor Family (Ice Lake) : <https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20200508> End users and systems administrators should check with their system manufacturers and system software vendors and apply any available updates as soon as practical. In addition, for Intel® SGX, Intel performed a TCB Recovery operation to enable parties utilizing SGX to determine whether the microcode version related to this Intel Security Advisory has been applied on the platform the SGX attestation request originated from. Intel has updated the Intel SGX Attestation Service (IAS) Dev environment on June 14th, 2019 and the IAS Production environment on July 12th, 2019, to return “GROUP_OUT_OF_DATE” response for affected platforms without the BIOS applied microcode update, and “CONFIGURATION_NEEDED” response for affected platforms that applied the microcode update through BIOS but with Intel® Hyper-Threading technology enabled. Additional Advisory Guidance on CVE-2018-12126, CVE-2018-12127, CVE-2018-12130, CVE-2019-11091 available [here](<https://software.intel.com/content/www/us/en/develop/topics/software-security-guidance.html>). ### Acknowledgements: Microarchitectural Store Buffer Data Sampling (MSBDS) - CVE-2018-12126: This vulnerability was found internally by Intel employees. Intel would like to thank Ke Sun, Henrique Kawakami, Kekai Hu and Rodrigo Branco. It was independently reported by Lei Shi - Qihoo - 360 CERT and by Marina Minkin1, Daniel Moghimi2, Moritz Lipp3, Michael Schwarz3, Jo Van Bulck4, Daniel Genkin1, Daniel Gruss3, Berk Sunar2, Frank Piessens4, Yuval Yarom5 (1University of Michigan, 2Worcester Polytechnic Institute, 3Graz University of Technology, 4imec-DistriNet, KU Leuven, 5University of Adelaide). Microarchitectural Load Port Data Sampling (MLPDS) - CVE-2018-12127: This vulnerability was found internally by Intel employees and Microsoft. Intel would like to thank Brandon Falk – Microsoft Windows Platform Security Team, Ke Sun, Henrique Kawakami, Kekai Hu, and Rodrigo Branco - Intel. It was independently reported by Matt Miller – Microsoft, and by Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida - VUSec group at VU Amsterdam. Microarchitectural Fill Buffer Data Sampling (MFBDS) - CVE-2018-12130: This vulnerability was found internally by Intel employees. Intel would like to thank Ke Sun, Henrique Kawakami, Kekai Hu and Rodrigo Branco. It was independently reported by Giorgi Maisuradze – Microsoft Research, and by Dan Horea Lutas, and Andrei Lutas - Bitdefender, and by Volodymyr Pikhur, and by Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida - VUSec group at VU Amsterdam, and by Moritz Lipp, Michael Schwarz, and Daniel Gruss - Graz University of Technology. Microarchitectural Data Sampling Uncacheable Memory (MDSUM) – CVE-2019-11091: This vulnerability was found internally by Intel employees. Intel would like to thank Ke Sun, Henrique Kawakami, Kekai Hu and Rodrigo Branco. It was independently found by Volodrmyr Pikhur, and by Moritz Lipp, Michael Schwarz, Daniel Gruss - Graz University of Technology, and by Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida - VUSec group at VU Amsterdam. Intel would like to thank Daniel Moghimi from Worcester Polytechnic Institute who provided Intel with a Proof of Concept (POC) in March 2020 for CVE-2018-12126 on 10th Generation Intel® Core™ Processor Family. Intel, and nearly the entire technology industry, follows a disclosure practice called Coordinated Disclosure, under which a cybersecurity vulnerability is generally publicly disclosed only after mitigations are available.


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