FIFO event channels control structure ordering

2020-12-15T12:00:00
ID XSA-359
Type xen
Reporter Xen Project
Modified 2020-12-15T12:19:00

Description

ISSUE DESCRIPTION

A bounds check common to most operation time functions specific to FIFO event channels depends on the CPU observing consistent state. While the producer side uses appropriately ordered writes, the consumer side isn't protected against re-ordered reads, and may hence end up de-referencing a NULL pointer.

IMPACT

Malicious or buggy guest kernels can mount a Denial of Service (DoS) attack affecting the entire system.

VULNERABLE SYSTEMS

All Xen versions from 4.4 onwards are vulnerable. Xen versions 4.3 and earlier are not vulnerable. Only Arm systems may be vulnerable. Whether a system is vulnerable will depend on the specific CPU. x86 systems are not vulnerable.