CR0.TS and CR0.EM not always honored for x86 HVM guests

ISSUE DESCRIPTION

Instructions touching FPU, MMX, or XMM registers are required to raise a Device Not Available Exception (#NM) when either CR0.EM or CR0.TS are set. (Their AVX or AVX-512 extensions would consider only CR0.TS.) While during normal operation this is ensured by the hardware, if a guest modifies instructions while the hypervisor is preparing to emulate them, the #NM delivery could be missed.
Guest code in one task may thus (unintentionally or maliciously) read or modify register state belonging to another task in the same VM.

IMPACT

A malicious unprivileged guest user may be able to obtain or corrupt sensitive information (including cryptographic material) in other programs in the same guest.

VULNERABLE SYSTEMS

All versions of Xen expose the vulnerabilty to their x86 HVM guests.
In order to exploit the vulnerability, the attacker needs to be able to trigger the Xen instruction emulator.
On Xen 4.7 the emulator can only be triggered: by user mode tasks which have been given access to memory-mapped IO; in guests which have been migrated between systems with CPUs from different vendors; or in guests which have been configured with a CPU vendor different from the host’s.
On Xen 4.6 and earlier, all HVM guests can trigger the emulator by attempting to execute an invalid opcode, exposing the vulnerability.
The vulnerability is only exposed to x86 HVM guests.
The vulnerability is not exposed to x86 PV or ARM guests.