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RedHat Linux
RedHat Linux
•added 2026/10/08 4:46 p.m.•17 views

kernel: KVM: SVM: Update x2APIC MSR intercepts if AVIC is inhibited while L2 is active

A flaw was found in KVM Kernel-based Virtual Machine. When the Advanced Virtual Interrupt Controller AVIC is inhibited while a nested guest L2 is active, KVM fails to properly update x2APIC MSR intercepts for the primary guest L1. This allows the L1 guest to read the host's APIC state, send...

8.2CVSS7.5AI score0.00135EPSS
SaveExploits0References5
AstraLinux
AstraLinux
•added 2026/10/05 11:39 a.m.•12 views

Astra Linux – Vulnerability in Linux 6.1

In the Linux kernel, the following vulnerability has been resolved: KVM: SVM: Update x2APIC MSR intercepts if AVIC is inhibited while L2 is active Always update x2APIC MSR intercepts for L1 when AVIC is deactivated, even if L2 is active and KVM uses a separate MSR bitmap to run L2. If AVIC is ful...

8.2CVSS6.1AI score0.00135EPSS
SaveExploits0References1
osv_azl
osv_azl
•added 2026/08/15 1:17 p.m.•24 views

AZL-96150 CVE-2026-74516 affecting package kernel for versions less than 6.6.152.1-1

In the Linux kernel, the following vulnerability has been resolved: KVM: SVM: Update x2APIC MSR intercepts if AVIC is inhibited while L2 is active Always update x2APIC MSR intercepts for L1 when AVIC is deactivated, even if L2 is active and KVM is using a separate MSR bitmap to run L2. If AVIC is...

8.2CVSS6.8AI score0.00135EPSS
SaveExploits0References1
osv_ubuntu
osv_ubuntu
•added 2026/08/15 1:17 p.m.•16 views

UBUNTU-CVE-2026-74516

In the Linux kernel, the following vulnerability has been resolved: KVM: SVM: Update x2APIC MSR intercepts if AVIC is inhibited while L2 is active Always update x2APIC MSR intercepts for L1 when AVIC is deactivated, even if L2 is active and KVM is using a separate MSR bitmap to run L2. If AVIC is...

8.2CVSS6.9AI score0.00135EPSS
SaveExploits0References9
CVE
CVE
•added 2026/08/15 12:27 p.m.•61 views

CVE-2026-74516

The CVE-2026-74516 issue affects the Linux kernel (KVM/SMV) where, if AVIC is inhibited while L2 is active, the host may run L1 with AVIC disabled and with x2APIC MSR intercepts also disabled. This allows L1 to access the host APIC state, trigger arbitrary interrupts, modify task priority, and co...

8.2CVSS6.8AI score0.00135EPSS
SaveExploits0References6
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