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SUSE CVE
SUSE CVE
•added 2026/09/19 1:37 a.m.•9 views

SUSE CVE-2026-93123

In the Linux kernel, the following vulnerability has been resolved: serial: qcom-geni: do not advance stale DMA completions The qcom GENI serial DMA TX completion path advances the transmit fifo by the number of bytes recorded in port-txremaining. If uartflushbuffer runs after the hardware has...

5.8AI score0.00209EPSS
SaveExploits0References3
Microsoft CVE
Microsoft CVE
•added 2025/09/04 4:50 a.m.•16 views

serial: sc16is7xx: fix TX fifo corruption

...

7.8CVSS7AI score0.00181EPSS
SaveExploits0
OSV
OSV
•added 2024/09/27 1:15 p.m.•7 views

DEBIAN-CVE-2024-46853

In the Linux kernel, the following vulnerability has been resolved: spi: nxp-fspi: fix the KASAN report out-of-bounds bug Change the memcpy length to fix the out-of-bounds issue when writing the data that is not 4 byte aligned to TX FIFO. To reproduce the issue, write 3 bytes data to NOR chip. dd...

7.8CVSS5.9AI score0.00243EPSS
SaveExploits0References1
OSV
OSV
•added 2024/09/27 1:15 p.m.•8 views

UBUNTU-CVE-2024-46853

In the Linux kernel, the following vulnerability has been resolved: spi: nxp-fspi: fix the KASAN report out-of-bounds bug Change the memcpy length to fix the out-of-bounds issue when writing the data that is not 4 byte aligned to TX FIFO. To reproduce the issue, write 3 bytes data to NOR chip. dd...

7.8CVSS6.8AI score0.00243EPSS
SaveExploits0References30
SUSE CVE
SUSE CVE
•added 2024/08/18 2:02 a.m.•9 views

SUSE CVE-2024-42279

In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rxlen == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the...

5.5CVSS7.1AI score0.00234EPSS
SaveExploits0References10
OSV
OSV
•added 2024/08/17 9:15 a.m.•14 views

UBUNTU-CVE-2024-42279

In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rxlen == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the...

7.8CVSS6.5AI score0.00234EPSS
SaveExploits0References11
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