Assertain: Automated Security Assertion Generation Using Large Language Models

The increasing complexity of modern system-on-chip designs amplifies hardware security risks and makes manual security property specification a major bottleneck in formal property verification. This paper presents Assertain, an automated framework that integrates RTL design analysis, Common...

LASA: Enhancing SoC Security Verification with LLM-Aided Property Generation

Ensuring the security of modern System-on-Chip SoC designs poses significant challenges due to increasing complexity and distributed assets across the intellectual property IP blocks. Formal property verification FPV provides the capability to model and validate design behaviors through security...