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OSV
OSV
added 2026/08/06 8:16 a.m.10 views

UBUNTU-CVE-2026-64592

In the Linux kernel, the following vulnerability has been resolved: riscv: mm: Unconditionally sfence.vma for spurious fault Svvptc does not guarantee that it's safe to just return here. Since we have already cleared our bit, if, theoretically, the bounded timeframe for the accessed page to becom...

5.3AI score0.00156EPSS
SaveExploits0References7
ATTACKERKB
ATTACKERKB
added 2026/08/06 7:13 a.m.11 views

CVE-2026-64592

In the Linux kernel, the following vulnerability has been resolved: riscv: mm: Unconditionally sfence.vma for spurious fault Svvptc does not guarantee that it's safe to just return here. Since we have already cleared our bit, if, theoretically, the bounded timeframe for the accessed page to becom...

5.4AI score0.00156EPSS
SaveExploits0References5Affected Software1
Cvelist
Cvelist
added 2026/08/06 7:13 a.m.40 views

CVE-2026-64592 riscv: mm: Unconditionally sfence.vma for spurious fault

In the Linux kernel, the following vulnerability has been resolved: riscv: mm: Unconditionally sfence.vma for spurious fault Svvptc does not guarantee that it's safe to just return here. Since we have already cleared our bit, if, theoretically, the bounded timeframe for the accessed page to becom...

0.00156EPSS
SaveExploits0References4
RedhatCVE
RedhatCVE
added 2025/11/11 12:50 p.m.11 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS7AI score0.00306EPSS
SaveExploits1References1
Cvelist
Cvelist
added 2025/11/10 12:00 a.m.20 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

0.00306EPSS
SaveExploits1References2
Vulnrichment
Vulnrichment
added 2025/11/10 12:00 a.m.7 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.6AI score0.00306EPSS
SaveExploits1References2
Positive Technologies
Positive Technologies
added 2025/11/10 12:00 a.m.18 views

PT-2025-46191

Name of the Vulnerable Software and Affected Versions RISC-V Rocket-Chip versions 1.6 and earlier Description A flaw exists in the handling of the SRET Supervisor-mode Exception Return instruction within the processor. Instead of correctly transitioning from Machine-mode M-mode to Supervisor-mode...

6.4AI score0.00306EPSS
SaveExploits1References5
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