9 matches found
Astra Linux – Vulnerability in Linux 5.10
In the Linux kernel, the following vulnerabilities have been resolved: perf: RISCV: Fix for panic occurring in the pmu overflow handler 1 idx of int is not desired when setting bits in unsigned long overflowctrs; use BIT instead. This panic occurs when running ‘perf record -e branches’ on sophgo...
Astra Linux - уязвимость в linux-5.10
In the Linux kernel, the following vulnerability has been resolved: riscv: cpuopssbi: Use static array for bootdata Since commit 6b9f29b81b15 "riscv: Enable pcpu page first chunk allocator", if NUMA is enabled, the page percpu allocator may be used on very sparse configurations, or when requested...
SUSE CVE-2025-38407
In the Linux kernel, the following vulnerability has been resolved: riscv: cpuopssbi: Use static array for bootdata Since commit 6b9f29b81b15 "riscv: Enable pcpu page first chunk allocator", if NUMA is enabled, the page percpu allocator may be used on very sparse configurations, or when requested...
DEBIAN-CVE-2025-38407
In the Linux kernel, the following vulnerability has been resolved: riscv: cpuopssbi: Use static array for bootdata Since commit 6b9f29b81b15 "riscv: Enable pcpu page first chunk allocator", if NUMA is enabled, the page percpu allocator may be used on very sparse configurations, or when requested...
UBUNTU-CVE-2025-38407
In the Linux kernel, the following vulnerability has been resolved: riscv: cpuopssbi: Use static array for bootdata Since commit 6b9f29b81b15 "riscv: Enable pcpu page first chunk allocator", if NUMA is enabled, the page percpu allocator may be used on very sparse configurations, or when requested...
SUSE CVE-2024-26902
In the Linux kernel, the following vulnerability has been resolved: perf: RISCV: Fix panic on pmu overflow handler 1 idx of int is not desired when setting bits in unsigned long overflowedctrs, use BIT instead. This panic happens when running 'perf record -e branches' on sophgo sg2042. 273.311852...
CVE-2024-26902
CVE-2024-26902 concerns the Linux kernel: a RISCV perf PMU overflow panic when setting bits for overflowed_ctrs due to using (1 <
CVE-2024-26902 perf: RISCV: Fix panic on pmu overflow handler
In the Linux kernel, the following vulnerability has been resolved: perf: RISCV: Fix panic on pmu overflow handler 1 idx of int is not desired when setting bits in unsigned long overflowedctrs, use BIT instead. This panic happens when running 'perf record -e branches' on sophgo sg2042. 273.311852...
CVE-2024-26902 perf: RISCV: Fix panic on pmu overflow handler
In the Linux kernel, the following vulnerability has been resolved: perf: RISCV: Fix panic on pmu overflow handler 1 idx of int is not desired when setting bits in unsigned long overflowedctrs, use BIT instead. This panic happens when running 'perf record -e branches' on sophgo sg2042. 273.311852...