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OSV
OSV
added 2026/05/12 5:16 p.m.12 views

UBUNTU-CVE-2025-35979

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some IntelR Processors within VMX non-root guest operation may allow an information disclosure. Unprivileged software adversary with an authenticated user combined with a...

6.8CVSS5.8AI score0.00096EPSS
SaveExploits0References4
RedHat Linux
RedHat Linux
added 2025/07/01 4:55 p.m.12 views

microcode_ctl: Exposure of sensitive information

Exposure of sensitive information caused by shared microarchitectural predictor state that influences transient execution for some Intel AtomR processors may allow an authenticated user to potentially enable information disclosure via local access...

5.7CVSS6.9AI score0.00189EPSS
SaveExploits0References5
OSV
OSV
added 2025/05/22 8:52 a.m.8 views

SUSE-SU-2025:01651-1 Security update for ucode-intel

This update for ucode-intel fixes the following issues: Intel CPU Microcode was updated to the 20250512 release bsc1243123 - CVE-2024-28956: Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel Processors may allow an authenticated us...

6.8CVSS6.9AI score0.00403EPSS
SaveExploits0References10
NVD
NVD
added 2025/05/13 9:15 p.m.10 views

CVE-2024-28956

Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some IntelR Processors may allow an authenticated user to potentially enable information disclosure via local access...

5.7CVSS0.00403EPSS
SaveExploits0References7
OSV
OSV
added 2025/05/13 9:15 p.m.8 views

ALPINE-CVE-2024-28956

Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some IntelR Processors may allow an authenticated user to potentially enable information disclosure via local access...

5.7CVSS7.5AI score0.00403EPSS
SaveExploits0References1
AlpineLinux
AlpineLinux
added 2025/05/13 9:02 p.m.9 views

CVE-2024-28956

Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some IntelR Processors may allow an authenticated user to potentially enable information disclosure via local access...

5.7CVSS6.4AI score0.00403EPSS
SaveExploits0
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