32 matches found
CVE-2025-63384
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
EUVD-2025-50785
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
CVE-2025-63384
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
CVE-2025-63384
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
Rocket Chip Generator 安全漏洞
Rocket Chip Generator is an open source Sysem-on-Chip design generator from CHIPS Alliance Open Source. A security vulnerability exists in Rocket Chip Generator v1.6 and earlier versions, which stems from a failure of the SRET instruction to properly convert processor privilege levels, which coul...
PT-2025-46191
Name of the Vulnerable Software and Affected Versions RISC-V Rocket-Chip versions 1.6 and earlier Description A flaw exists in the handling of the SRET Supervisor-mode Exception Return instruction within the processor. Instead of correctly transitioning from Machine-mode M-mode to Supervisor-mode...
CVE-2025-63384
The RISC-V Rocket-Chip (version 1.6 and earlier) contains a privilege retention vulnerability due to a flaw in the SRET (Supervisor-mode Exception Return) instruction handling. The processor fails to correctly transition from Machine-mode (M-mode) to Supervisor-mode (S-mode) as required by the ss...
CVE-2025-63384: Incorrect Privilege Assignment
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
CVE-2025-63384
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
CVE-2025-63384
A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...
EUVD-2022-37584
Malicious code in bioql PyPI...
EUVD-2025-31738
Malicious code in bioql PyPI...
CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...
CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...
CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...
CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...
CVE-2025-56301
An issue was discovered in the Chipsalliance Rocket-Chip generator (commit f517abbf41abb65cea37421d3559f9739efd00a9 ) involving a flawed interaction between exception handling and MRET (Machine Return) mechanisms within the CSR (Control and Status Register) logic. When the MRET instruction is exe...
PT-2025-39994
Name of the Vulnerable Software and Affected Versions Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 Description An issue exists in the Control and Status Register CSR logic that allows attackers to corrupt exception handling and privilege state transitions. This occurs du...
Rocket Chip Generator 安全漏洞
Rocket Chip Generator is an open source Sysem-on-Chip design generator from CHIPS Alliance Open Source. A security vulnerability exists in Rocket Chip Generator, which stems from flaws in the exception handling and MRET return mechanisms that could result in conflicting updates to the control sta...
CVE-2025-56301
An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...