riscy-business

riscy-business Article:RISC-Y Business: Raging against the reduced machine. Prerequisites Visual Studio 2022 with the C++ Clang Compiler for Windows 16.0.5 component CMake 3.26 earlier may work, but not recommended riscvm This folder contains the VM host rv64i interpreter. To build: cd riscvm cma...

CLEANSTART-2026-YQ62547 Issue summary: A non-constant-time optimized implementation of scalar point multiplication is used for SM2 private key operations on ARM64 and RISC-V platforms

CVE-2026-54875 affects multiple packages. Issue summary: A non-constant-time optimized implementation of scalar point multiplication is used for SM2 private key operations on ARM64 and RISC-V platforms. See references for individual vulnerability details...

riscv-isa-sim

Spike RISC-V ISA Simulator About Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. It is named after the golden spike used to celebrate the completion of the US transcontinental railway. Spike supports the following RISC-V ISA features: RV32I and RV64I ba...

Reverse-Engineering

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures. FREE EMBEDDED HACKING COURSE PROMO HERE Join DC540 Discord HERE Today's Tutorial October 21, 2026 Lesson 332: Hacking Bits Course Chapter 10: STUXNET This chapter...

arduino-pico

Arduino-Pico Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards This is a port of Arduino to the RP2040 Raspberry Pi Pico processor and RP2350 Raspberry Pi Pico 2 processor. It uses the bare Raspberry Pi Pico SDK and a custom GCC 16.1/Newlib 4.6 toolchain and supports ARM and RISC-V...

sfuzz

SFUZZ Start date: Dec, 2021 This is a coverage-guided, emulation based greybox fuzzer that makes use of a custom Just-In-Time compiler to achieve near-native performance. It works by lifting RISC-V elf binaries to an intermediate representation before JIT compiling them to x86 during execution...

GoTEE

Introduction The GoTEE framework implements concurrent instantiation of TamaGo based unikernels in privileged and unprivileged modes, interacting with each other through monitor mode and custom system calls. With these capabilities GoTEE implements a TamaGo based Trusted Execution Environments TE...

ckb-vm

Nervos CKB VM About CKB VM CKB VM is a pure software implementation of the RISC-V instruction set used as scripting VM in CKB. Right now it implements full IMCB instructions for both 32-bit and 64-bit register size support. In the future we might also implement V extensions to enable better crypt...

CVE-2026-98639

A flaw was found in the Linux kernel's KVM Kernel-based Virtual Machine subsystem for the RISC-V architecture. During nested virtualization acceleration, control flags are written before the target page parameters are properly committed to shared memory. Consequently, the supervisor interface or...

CVE-2026-93132

A flaw was found in the Linux kernel's Advanced Configuration and Power Interface ACPI implementation for RISC-V architectures. Specifically, the riscvacpiaddprtdep function contains a loop that incorrectly handles error conditions. This can cause the loop to skip necessary entry pointer updates,...

CVE-2026-92518

A flaw was found in the Linux kernel's RISC-V BPF JIT compiler. When Control-Flow Integrity CFI with Clang is enabled, an error in calculating the tail call jump offset can lead to kernel stack corruption. This issue causes the system to improperly adjust the stack pointer, which can result in...

CVE-2026-92517

A flaw was found in the Linux kernel's Berkeley Packet Filter BPF subsystem, specifically in the handling of extable entries for arena loadacquire operations on RISC-V architecture. Due to improper exception handling, a stale register value on fault can be leaked through a map, potentially leadin...

EUVD-2026-104600

The OSDP Control Panel reply parser cpdecoderesponse in subsys/mgmt/osdp/src/osdpcp.c decodes replies from a Peripheral Device into a stack-allocated struct osdpevent. For the REPLYKEYPPAD and REPLYRAW reply types, the payload length is taken from the received frame and the only validation...

CVE-2026-98465

A flaw was found in the Linux kernel's Kernel-based Virtual Machine KVM subsystem for the RISC-V architecture. Due to missing synchronization between interrupt controller device operations and virtual CPU vCPU execution, a local user with access to the KVM interface can trigger a race condition...

CVE-2026-98464

A flaw was found in the Linux kernel's KVM Kernel-based Virtual Machine implementation for the RISC-V architecture. This vulnerability can lead to a Denial of Service DoS or host system crash due to a use-after-free memory issue during virtual machine teardown. A race condition allows a timer...

zirgen

Zirgen Circuit Compiler Zirgen is a compiler for a domain-specific language, also called "zirgen", which creates arithmetic circuits for the RISC Zero proof system. For the most part, users of RISC Zero should be writing their zkApps in Rust and using our RISC-V zkVM rather than building them...

pico2-swd-riscv

pico2-swd-riscv SWD debug probe for RP2350 RISC-V Hazard3 cores. One Pico2 debugs another via two GPIO wires. 0. VIBE CODE WARNING WRITTEN BY HUMAN About 80% of the code is vibe coded; The readme is almost completely generated except the whole vibe-code-warning section. I spent many nights with...

boxlambda

About BoxLambda BoxLambda is a hardware-software crossover project creating a homebrew, retro-style FPGA-based microcomputer. The goal is to create a sandbox environment for experimenting with software and FPGA gateware. The Physical Setup The physical setup. Current Features Target FPGA:...

vpod

Vpod Live demo • Getting Started • Documentation • Issues • Contributing What is a vpod ? A vpod is a lightweight, portable sandbox that gives an untrusted process an instant Linux environment. It uses a RISC‑V architecture and runs entirely inside WebAssembly. Fast startup : Boot in under a...

CVE-2026-98465

In the Linux kernel, the following vulnerability has been resolved: RISC-V: KVM: Serialize IMSIC attributes with vCPU migration KVM device ioctls are not serialized against KVMRUN. As a result, kvmriscvaiaimsicrwattr can snapshot the physical CPU and HGEI of an IMSIC VS-file before a concurrent...