CVE-2025-51679: Sequence of Processor Instructions Leads to Unexpected Behavior

An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...

Astra Linux – Vulnerability in Linux 5.10

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit, 8c30b0018f9d “openrisc: Add jump label support”, copied from arm64 and did not properly account for how icache invalidation operates on remote cores in OpenRISC. On OpenRIS...

CVE-2026-72154

A flaw was found in the Linux kernel, specifically within the OpenRISC architecture's handling of jump label synchronization in Symmetric Multiprocessing SMP systems. The implementation did not correctly invalidate instruction caches icaches on remote processor cores after updates. This oversight...

Linux Distros Unpatched Vulnerability : CVE-2026-72154

The Linux/Unix host has one or more packages installed that are impacted by a vulnerability without a vendor supplied patch available. - In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d openrisc: Add jump labe...

CVE-2026-72154

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

UBUNTU-CVE-2026-72154

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

CVE-2026-72154

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

CVE-2026-72154 openrisc: Fix jump_label smp syncing

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

EUVD-2026-58912

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

CVE-2026-72154

CVE-2026-72154 describes a Linux kernel vulnerability in the OpenRISC path related to jump_label SMP cache syncing. The issue arose from an OpenRISC-specific implementation that copied from arm64 and didn’t correctly handle icache invalidation on remote cores, which could leave stale static_key c...

CVE-2026-72154 openrisc: Fix jump_label smp syncing

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

CVE-2026-72154: Undefined Security Weakness

In the Linux kernel, the following vulnerability has been resolved: openrisc: Fix jumplabel smp syncing The original commit 8c30b0018f9d "openrisc: Add jump label support" copies from arm64 and does not properly consider how icache invalidation on remote cores works in OpenRISC. On OpenRISC remot...

PT-2026-72342

Name of the Vulnerable Software and Affected Versions Linux kernel affected versions not specified Description An issue exists in the OpenRISC architecture implementation regarding jump label SMP syncing. The system fails to properly invalidate instruction caches icaches on remote cores, which ca...

CVE-2025-51677

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...

CVE-2025-51677

An issue was discovered in openRISC OR1200 commit 83ac6b where an output mismatch exists between the RTL and the netlist of the OR1200 CPU output port. This discrepancy can lead to unexpected behavior . No specific exploit details or remediation steps are provided in the documents.

CVE-2025-51677

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...

CVE-2025-51677

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...

CVE-2025-51677: Improper Encoding or Escaping of Output

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...

CVE-2025-51677

An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...

PT-2026-60840

Name of the Vulnerable Software and Affected Versions openRISC OR1200 commit 83ac6b Description An output mismatch exists between the Register Transfer Level RTL, which is a high-level description of the electronic circuit, and the netlist, which is a detailed description of the circuit's...