HAL -- an Open-Source Framework for Gate-Level Netlist Analysis

HAL is an open-source framework for gate-level netlist analysis, an integral step in hardware reverse engineering. It provides analysts with an interactive GUI, an extensible plugin system, and APIs in both C++ and Python for rapid prototyping and automation. In addition, HAL ships with plugins f...

Automated Hardware Trojan Insertion in Industrial-Scale Designs

Industrial Systems-on-Chips SoCs often comprise hundreds of thousands to millions of nets and millions to tens of millions of connectivity edges, making empirical evaluation of hardware-Trojan HT detectors on realistic designs both necessary and difficult. Public benchmarks remain significantly...

PoSyn: Secure Power Side-Channel Aware Synthesis

Power Side-Channel PSC attacks exploit power consumption patterns to extract sensitive information, posing risks to cryptographic operations crucial for secure systems. Traditional countermeasures, such as masking, face challenges including complex integration during synthesis, substantial area...

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs

In the evolving landscape of integrated circuit IC design, the increasing complexity of modern processors and intellectual property IP cores has introduced new challenges in ensuring design correctness and security. The recent advancements in hardware fuzzing techniques have shown their efficacy ...

[SECURITY] Fedora 10 Update: geda-gnetlist-20080929-2.fc10

Gnetlist generates netlists from schematics drawn with gschem the gEDA schematic editor. Possible output formats are: - native - tango - spice - allegro - PCB - verilog and others...

[SECURITY] Fedora 9 Update: geda-gnetlist-20080929-2.fc9

Gnetlist generates netlists from schematics drawn with gschem the gEDA schematic editor. Possible output formats are: - native - tango - spice - allegro - PCB - verilog and others...