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7 matches found

EUVD
EUVD
added 2026/04/21 12:32 a.m.1 views

EUVD-2026-23957

XiangShan Open-source high-performance RISC-V processor commit edb1dfaf7d290ae99724594507dc46c2c2125384 2024-11-28 contains an improper exceptional-condition handling flaw in its CSR subsystem NewCSR. On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR...

6AI score0.00006EPSS
Exploits0References5
Cvelist
Cvelist
added 2026/04/20 12:0 a.m.17 views

CVE-2026-29643

XiangShan Open-source high-performance RISC-V processor commit edb1dfaf7d290ae99724594507dc46c2c2125384 2024-11-28 contains an improper exceptional-condition handling flaw in its CSR subsystem NewCSR. On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR...

0.00006EPSS
Exploits0References4
Positive Technologies
Positive Technologies
added 2026/04/20 12:0 a.m.1 views

PT-2026-33855

XiangShan Open-source high-performance RISC-V processor commit edb1dfaf7d290ae99724594507dc46c2c2125384 2024-11-28 contains an improper exceptional-condition handling flaw in its CSR subsystem NewCSR. On affected versions, certain sequences of CSR operations targeting non-existent/custom CSR...

7.1CVSS6AI score0.00006EPSS
Exploits0References6
RedhatCVE
RedhatCVE
added 2025/05/22 9:17 p.m.7 views

CVE-2021-1104

The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address MTVEC register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of servic...

9.8CVSS6.8AI score0.00566EPSS
Exploits1References1
NVD
NVD
added 2021/08/13 4:15 p.m.7 views

CVE-2021-1104

The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address MTVEC register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of servic...

9.8CVSS0.00566EPSS
Exploits1References1
Cvelist
Cvelist
added 2021/08/13 3:40 p.m.11 views

CVE-2021-1104

The RISC-V Instruction Set Manual contains a documented ambiguity for the Machine Trap Vector Base Address MTVEC register that may lead to a vulnerability due to the initial state of the register not being defined, potentially leading to information disclosure, data tampering and denial of servic...

9.4AI score0.00566EPSS
Exploits1References1
CVE
CVE
added 2021/08/13 3:40 p.m.69 views

CVE-2021-1104

The CVE-2021-1104 entry relates to the RISC-V Instruction Set Manual, where an ambiguity in the Machine Trap Vector Base Address (MTVEC) register’s initial state is not defined. This ambiguity is stated to potentially enable information disclosure, data tampering, and denial of service. The conso...

9.8CVSS9.1AI score0.00566EPSS
Exploits1References1Affected Software1
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