Incorrect Privilege Assignment

Overview Affected versions of this package are vulnerable to Incorrect Privilege Assignment due to improper retention of the mstatus.SUM bit, which remains set contrary to privileged specification constraints. An attacker can gain unauthorized access to physical memory by exploiting this improper...

RISC-V Processor 安全漏洞

RISC-V Processor is an instruction set architecture from the Swiss company RISC-V. A security vulnerability exists in RISC-V Processor that stems from an improperly reserved mstatus.SUM bit leading to a physical memory access attack...