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NVD
NVD
•added 2026/04/20 8:16 p.m.•17 views

CVE-2026-29649

NEMU contains an implementation flaw in its RISC-V Hypervisor CSR handling where henvcfg7:4 CBIE/CBCFE/CBZE-related fields is incorrectly masked/updated based on menvcfg7:4, so a machine-mode write to menvcfg can implicitly modify the hypervisor's environment configuration. This can lead to...

9.8CVSS0.00661EPSS
SaveExploits0References4
attackerkb
attackerkb
•added 2026/04/20 12:00 a.m.•8 views

CVE-2026-29649

NEMU contains an implementation flaw in its RISC-V Hypervisor CSR handling where henvcfg7:4 CBIE/CBCFE/CBZE-related fields is incorrectly masked/updated based on menvcfg7:4, so a machine-mode write to menvcfg can implicitly modify the hypervisor's environment configuration. This can lead to...

5.7AI score0.00661EPSS
SaveExploits0References5
RedhatCVE
RedhatCVE
•added 2025/11/11 12:50 p.m.•17 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS7AI score0.00306EPSS
SaveExploits1References1
EUVD
EUVD
•added 2025/11/10 9:30 p.m.•16 views

EUVD-2025-50785

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5AI score0.00306EPSS
SaveExploits1References3
NVD
NVD
•added 2025/11/10 8:15 p.m.•19 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS0.00306EPSS
SaveExploits1References2
CVE
CVE
•added 2025/11/10 12:00 a.m.•40 views

CVE-2025-63384

The RISC-V Rocket-Chip (version 1.6 and earlier) contains a privilege retention vulnerability due to a flaw in the SRET (Supervisor-mode Exception Return) instruction handling. The processor fails to correctly transition from Machine-mode (M-mode) to Supervisor-mode (S-mode) as required by the ss...

6.5CVSS5.8AI score0.00306EPSS
SaveExploits1References2Affected Software1
Positive Technologies
Positive Technologies
•added 2025/11/10 12:00 a.m.•27 views

PT-2025-46191

Name of the Vulnerable Software and Affected Versions RISC-V Rocket-Chip versions 1.6 and earlier Description A flaw exists in the handling of the SRET Supervisor-mode Exception Return instruction within the processor. Instead of correctly transitioning from Machine-mode M-mode to Supervisor-mode...

6.4AI score0.00306EPSS
SaveExploits1References5
Vulnrichment
Vulnrichment
•added 2025/11/10 12:00 a.m.•10 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

5.8AI score0.00306EPSS
SaveExploits1References2
OSV
OSV
•added 2025/11/10 12:00 a.m.•10 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS5.4AI score
SaveExploits0References4
EUVD
EUVD
•added 2025/10/03 8:07 p.m.•13 views

EUVD-2025-31738

Malicious code in bioql PyPI...

7.5CVSS6.6AI score0.00641EPSS
SaveExploits1References6
Cvelist
Cvelist
•added 2025/09/30 12:00 a.m.•27 views

CVE-2025-56301

An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...

0.00641EPSS
SaveExploits1References5
CVE
CVE
•added 2025/09/30 12:00 a.m.•76 views

CVE-2025-56301

An issue was discovered in the Chipsalliance Rocket-Chip generator (commit f517abbf41abb65cea37421d3559f9739efd00a9 ) involving a flawed interaction between exception handling and MRET (Machine Return) mechanisms within the CSR (Control and Status Register) logic. When the MRET instruction is exe...

7.5CVSS6.8AI score0.00641EPSS
SaveExploits1References5Affected Software1
Positive Technologies
Positive Technologies
•added 2025/09/30 12:00 a.m.•26 views

PT-2025-39994

Name of the Vulnerable Software and Affected Versions Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 Description An issue exists in the Control and Status Register CSR logic that allows attackers to corrupt exception handling and privilege state transitions. This occurs du...

7.5CVSS6.5AI score0.00641EPSS
SaveExploits1References10
Citrix
Citrix
•added 2024/07/13 12:00 a.m.•13 views

Troubleshooting Linux Virtual Machines in XenServer

This article describes about troubleshooting Linux virtual machines in XenServer. Serial console was used to access UNIX server consoles and most of the network devices switches, routes. The simplicity of serial port hardware and its universality make them popular. Serial console apart from...

6.8AI score
SaveExploits0
OSV
OSV
•added 2017/01/23 9:59 p.m.•13 views

UBUNTU-CVE-2016-9382

Xen 4.0.x through 4.7.x mishandle x86 task switches to VM86 mode, which allows local 32-bit x86 HVM guest OS users to gain privileges or cause a denial of service guest OS crash by leveraging a guest operating system that uses hardware task switching and allows a new task to start in VM86 mode...

7.8CVSS7.1AI score0.00452EPSS
SaveExploits0References3
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