AtomicMemory

Reference FPGA Implementation Cyclone V This directory contains the reference RTL modules, precompiled FPGA images, and optional TCL test scripts for the atomic measurement–collapse primitive. This primitive is a CMOS-compatible hardware measurement–collapse mechanism that enforces single-read...

amradio

AM Radio Break-in System A 12-channel AM radio broadcast system using Red Pitaya FPGA for emergency alert transmission in unmanned tunnels. Why AM radio in a tunnel? During construction and maintenance, vehicles with standard AM radios transit through tunnels that have no mobile coverage. AM...

nextpnr

nextpnr -- a portable FPGA place and route tool nextpnr aims to be a vendor neutral, timing driven, FOSS FPGA place and route tool. Currently nextpnr supports: Lattice iCE40 devices supported by Project IceStorm Lattice ECP5 devices supported by Project Trellis Lattice Nexus devices supported by...

s6_pcie_microblaze

PCI Express DIY hacking toolkit General information Contents SP605 board configuration Software configuration Examples Using Python API Practical DMA attacks Option ROM attacks Troubleshooting Building project from the source code General information This repository contains a set of tools and...

proxmark3

proxmark3: the official Proxmark repository! ⚠️ This repository has been archived. It is no longer maintained. Active development has moved over to RRG Proxmark3 - Iceman Fork The proxmark3 is a powerful general purpose RFID tool, the size of a deck of cards, designed to snoop, listen and emulate...

BTLE

BTLE BTLE is a free and open-source Bluetooth Low Energy BLE Software Defined Radio software suite and open BTLE chip design. It includes: BTLE baseband algorithms description, Python and Verilog implementation, FPGA and SkyWater 130 PDK OpenLane2 workflow results. Analog Devices AD9361 + Xilinx...

boxlambda

About BoxLambda BoxLambda is a hardware-software crossover project creating an experimental, retro-style, FPGA-based microcomputer. The goal is to create a new computer to explore old ideas. The Physical Setup The physical setup. Current Features Target FPGA: Arty-A7-100T. Ibex RISC-V core with...

aegis

Aegis Aegis is a fully open-source FPGA, from the silicon up. Open-source FPGA efforts have made huge strides: projects like Project IceStorm and Apicula reverse-engineer proprietary bitstream formats, OpenFPGA and FABulous generate open FPGA fabric from architecture descriptions, and Cologne...

phywhispererusb

PhyWhisperer-USB What is this thing? This is a hardware trigger for FI or SCA, which triggers on the USB phy. Be sure to read the documentation at http://phywhispererusb.readthedocs.io/ as well! If you are getting started, there are a few demonstration notebooks showing how to: Sniff Data Stream...

Security update for the Linux Kernel

The SUSE Linux Enterprise 12 SP5 kernel was updated to fix various security issues: The following security issues were fixed: CVE-2023-54158: btrfs: don't free qgroup space unless specified bsc1256076. CVE-2023-54180: btrfs: handle case when repair happens with dev-replace bsc1255995...

MicroC-u-os2-vuln-code-extracted-from-

MicroC-u-os2-vuln-code-extracted-from- Buffer Overflow Attack and Prevention for an FPGA Based Soft-Processor System - 7th International Conference on Innovation in Electronics and Communication EngineeringICIECE'18...

HAWC-Leak: Heterogeneous Architecture Workload Classification Utilizing Side-Channel Leakage

Modern heterogeneous computing platforms, which integrate general-purpose processors with specialized accelerators such as FPGAs, have become the standard for high-performance and embedded applications. However, the shared physical resources of these systems introduce critical security...

A Combined Streaming FPGA Architecture for Client-Side CKKS Encoding and Encryption

Homomorphic encryption allows a computing service to process encrypted data, but the client must first encode and encrypt its inputs. Sharing hardware between floating-point encoding and modular encryption reduces area but requires those transform roles to execute at different times. We present a...

DMA-ProcessDumper

DMA-ProcessDumper Dumps entire memory of target process on the user-mode using DMA with MemProcFS over a PCIe FPGA device Building Copy leechcore.h, vmmdll.h and vmm.lib from MemProcFS into the DMA-ProcessDumper directory Compile using Visual Studio Copy leechcore.dll, vmm.dll and FTD3XX.dll from...

Astra Linux – Vulnerabilities in Linux 5.10, Linux 5.15, Linux 6.1

In the Linux kernel, the following vulnerability has been resolved: fpga: region: adding an owner module and taking its reference count The current implementation of the fpga region assumes that the low-level module registers a driver for the parent device and uses its owner pointer to take the...

Astra Linux – Vulnerability in Linux 6.1

In the Linux kernel, the following vulnerabilities have been resolved: fpga: microchip-spi: fixed the issue where zero headersize OOB read was performed in mpfopsParseHeader. The mpfopsParseHeader function reads headersize from the bitstream at MPFHEADERSIZEOFFSET 24. When headersize is zero, the...

Application Agnostic EM Side-Channel Emanations of the FPGA Clock Distribution Network

Electromagnetic side channels have been extensively utilized in non-invasive attacks or analyses to extract critical information from deployed systems. Most of the attacks or analyses are typically executed on cryptographic algorithms under the assumption that the underlying implementation remain...

SUSE CVE-2026-89730

In the Linux kernel, the following vulnerability has been resolved: fpga: altera-cvp: Avoid out-of-bounds read in trailing byte write The trailing byte path in alteracvpsendblock dereferences a u32 pointer even when only 1-3 bytes remain in the input buffer. If the buffer ends at a page or...

FSNIC: A Low-Latency Flow-Based Intrusion Detection Architecture for FPGA SmartNICs

Modern data centres require high-performance networking alongside effective real-time security. Traditional Intrusion Detection Systems IDS commonly rely on general-purpose processors and often struggle to inspect high-speed traffic at line rate without introducing latency or performance...

A High-Throughput FPGA Architecture for Real-Time TCP-SYN Scan Detection

TCP-SYN port scanning often precedes cyber-attacks, and early detection of scanner fingerprints embedded in packet headers can provide timely intrusion alerts. Existing approaches are either too computationally expensive for line-rate operation or limited to offline analysis. This brief presents ...