CVE-2025-45006

Improper mstatus.SUM bit retention non-zero in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks...

edu.berkeley.cs:rocket-dsptools_2.12 (>=1.2.0 <=1.2.6) potentially affected by CVE-2025-45006 via edu.berkeley.cs:rocketchip_2.12 (>=1.2.0-RC1 <=1.2.6)

edu.berkeley.cs:rocketchip2.12 MAVEN version =1.2.0-RC1, =1.2.0, =1.2.6 Source cves: CVE-2025-45006 Source advisory: SNYK:JAVA-EDUBERKELEYCS-11188144...

CVE-2025-45006

Improper mstatus.SUM bit retention non-zero in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks...

CVE-2025-45006

Improper mstatus.SUM bit retention non-zero in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks...

CVE-2025-45006

Improper mstatus.SUM bit retention non-zero in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks...

CVE-2025-45006

Improper mstatus.SUM bit retention non-zero in Open-Source RISC-V Processor commit f517abb violates privileged spec constraints, enabling potential physical memory access attacks...

CVE-2025-45006

The CVE-2025-45006 entry concerns an issue in the Open-Source RISC-V Processor where the mstatus.SUM bit can remain non-zero, violating privileged-spec constraints. Root cause identified as improper retention in commit f517abb, enabling potential physical memory access attacks. Affected component...