CVE-2025-56301

An issue was discovered in the Chipsalliance Rocket-Chip generator (commit f517abbf41abb65cea37421d3559f9739efd00a9 ) involving a flawed interaction between exception handling and MRET (Machine Return) mechanisms within the CSR (Control and Status Register) logic. When the MRET instruction is exe...

CVE-2025-56301: Sequence of Processor Instructions Leads to Unexpected Behavior

An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...