11 matches found
CVE-2025-51679
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...
CVE-2025-51679
A vulnerability was identified in openRISC OR1200 (commit 83ac6b ). The root cause is a mismatch between the RTL and netlist , which can result in unexpected behavior . Specific exploit details are not provided in the documents, though the issue has been sighted in the wild. No specific remediati...
EUVD-2025-210801
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...
CVE-2025-51679: Sequence of Processor Instructions Leads to Unexpected Behavior
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...
EUVD-2025-210799
An issue was discovered in openRISC OR1200 commit 83ac6b. An inaccurate update of program counter PC values when SPR changes can lead to a Denial of Service DoS...
CVE-2025-51679
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...
PT-2026-82287
An issue was discovered in openRISC OR1200 commit 83ac6b. A mismatch between the RTL and netlist can lead to unexpected behavior...
CVE-2025-51677
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...
CVE-2025-51677: Improper Encoding or Escaping of Output
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...
CVE-2025-51677
An issue was discovered in openRISC OR1200 commit 83ac6b. An output mismatch between the RTL and the netlist of the or1200 cpu output port can lead to unexpected behavior...
PT-2026-60840
Name of the Vulnerable Software and Affected Versions openRISC OR1200 commit 83ac6b Description An output mismatch exists between the Register Transfer Level RTL, which is a high-level description of the electronic circuit, and the netlist, which is a detailed description of the circuit's...