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AstraLinux
AstraLinux
•added 2026/06/24 3:11 p.m.•16 views

Astra Linux – Vulnerability found in Linux 6.1, Linux 6.12

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will result in a broken link. The Rockchip DWC MSHC controller...

5.5CVSS6.2AI score0.00133EPSS
SaveExploits0References3
SUSE CVE
SUSE CVE
•added 2026/02/17 12:26 a.m.•41 views

SUSE CVE-2025-71200

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

5.5CVSS6.1AI score0.00133EPSS
SaveExploits0References19
OSV
OSV
•added 2026/02/14 3:09 p.m.•19 views

CVE-2025-71200 mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

5.3AI score
SaveExploits0References8
attackerkb
attackerkb
•added 2026/02/14 3:09 p.m.•14 views

CVE-2025-71200

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

6.2AI score0.00133EPSS
SaveExploits0References6Affected Software1
Cvelist
Cvelist
•added 2026/02/14 3:09 p.m.•54 views

CVE-2025-71200 mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

0.00133EPSS
SaveExploits0References5
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