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AstraLinux
AstraLinux
added 2026/05/03 11:59 p.m.5 views

Astra Linux - уязвимость в linux-5.10

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will cause the link to break. The Rockchip DWC MSHC controller...

5.5CVSS5.7AI score0.00018EPSS
Exploits0References1
SUSE CVE
SUSE CVE
added 2026/02/17 12:26 a.m.4 views

SUSE CVE-2025-71200

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

5.5CVSS5.2AI score0.00018EPSS
Exploits0References19
ATTACKERKB
ATTACKERKB
added 2026/02/14 3:9 p.m.2 views

CVE-2025-71200

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

5.2AI score0.00018EPSS
Exploits0References6Affected Software1
Cvelist
Cvelist
added 2026/02/14 3:9 p.m.21 views

CVE-2025-71200 mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

0.00018EPSS
Exploits0References5
OSV
OSV
added 2026/02/14 3:9 p.m.3 views

CVE-2025-71200 mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode

In the Linux kernel, the following vulnerability has been resolved: mmc: sdhci-of-dwcmshc: Prevent illegal clock reduction in HS200/HS400 mode When operating in HS200 or HS400 timing modes, reducing the clock frequency below 52MHz will lead to link broken as the Rockchip DWC MSHC controller...

5.5CVSS5.3AI score0.00018EPSS
Exploits0References8
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