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6 matches found

EUVD
EUVD
added 2026/05/27 3:33 p.m.13 views

EUVD-2026-32229

In the Linux kernel, the following vulnerability has been resolved: iommu/vt-d: Fix race condition during PASID entry replacement The Intel VT-d PASID table entry is 512 bits 64 bytes. When replacing an active PASID entry e.g., during domain replacement, the current implementation calculates a ne...

5.8AI score0.00128EPSS
Exploits0References3
UbuntuCve
UbuntuCve
added 2026/05/27 12:0 a.m.9 views

CVE-2026-45862

iommu/vt-d: Flush cache for PASID table before using it...

7.8CVSS5.8AI score0.00149EPSS
Exploits0References2
ATTACKERKB
ATTACKERKB
added 2026/05/06 11:28 a.m.11 views

CVE-2026-43248

In the Linux kernel, the following vulnerability has been resolved: vhost: move vdpa group bound check to vhostvdpa Remove duplication by consolidating these here. This reduces the posibility of a parent driver missing them. While we're at it, fix a bug in vdpasim where a valid ASID can be assign...

5.8AI score0.00129EPSS
Exploits0References5Affected Software1
ATTACKERKB
ATTACKERKB
added 2026/04/22 1:53 p.m.4 views

CVE-2026-31462

In the Linux kernel, the following vulnerability has been resolved: drm/amdgpu: prevent immediate PASID reuse case PASID resue could cause interrupt issue when process immediately runs into hw state left by previous process exited with the same PASID, it's possible that page faults are still...

5.7AI score0.00122EPSS
Exploits0References5Affected Software1
Vulnrichment
Vulnrichment
added 2026/02/10 7:8 p.m.4 views

CVE-2025-48517

Insufficient Granularity of Access Control in SEV firmware could allow a privileged user with a malicious hypervisor to create a SEV-ES guest with an ASID in the range meant for SEV-SNP guests potentially resulting in a partial loss of confidentiality...

4.6CVSS5.5AI score0.00136EPSS
Exploits0References1
OSV
OSV
added 2025/05/20 4:15 p.m.2 views

DEBIAN-CVE-2025-37964

In the Linux kernel, the following vulnerability has been resolved: x86/mm: Eliminate window where TLB flushes may be inadvertently skipped tl;dr: There is a window in the mm switching code where the new CR3 is set and the CPU should be getting TLB flushes for the new mm. But shouldflushtlb has a...

5.5CVSS5.8AI score0.00149EPSS
Exploits0References1
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