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Positive Technologies
Positive Technologies
added 2026/05/08 12:0 a.m.7 views

PT-2026-38949

Name of the Vulnerable Software and Affected Versions Linux kernel affected versions not specified Description An issue exists in the adxl380 accelerometer driver where the interrupt handler reads FIFO entries in batches of N samples, based on the number of enabled scan elements. Because the sens...

7.8CVSS5.8AI score0.00013EPSS
Exploits0References7
Cvelist
Cvelist
added 2026/04/21 12:0 a.m.25 views

CVE-2026-29644

XiangShan open-source high-performance RISC-V processor commit edb1dfaf7d290ae99724594507dc46c2c2125384 2024-11-28 has improper gating of its distributed CSR write-enable path, allowing illegal CSR write attempts to alter custom PMA Physical Memory Attribute CSR state. Though the RISC-V privilege...

0.00014EPSS
Exploits0References5
EUVD
EUVD
added 2026/04/20 9:31 p.m.1 views

EUVD-2026-23960

In OpenXiangShan NEMU, insufficient Smstateen permission enforcement allows lower-privileged code to access IMSIC state via stopei/vstopei CSRs even when mstateen0.IMSIC is cleared, potentially enabling cross-context information leakage or disruption of interrupt handling...

5.8AI score0.00034EPSS
Exploits0References4
Positive Technologies
Positive Technologies
added 2026/04/20 12:0 a.m.2 views

PT-2026-33840

In OpenXiangShan NEMU, insufficient Smstateen permission enforcement allows lower-privileged code to access IMSIC state via stopei/vstopei CSRs even when mstateen0.IMSIC is cleared, potentially enabling cross-context information leakage or disruption of interrupt handling...

6.5CVSS5.8AI score0.00034EPSS
Exploits0References5
CVE
CVE
added 2026/04/20 12:0 a.m.2 views

CVE-2026-29643

The CVE relates to XiangShan’s CSR subsystem (NewCSR) in an open‑source RISC‑V processor. The flaw is an improper exceptional‑condition handling when CSR operations target non‑existent/custom CSR addresses, which may trigger an illegal‑instruction exception but fail to reliably transfer control t...

7.1CVSS6AI score0.00006EPSS
Exploits0References4
Cvelist
Cvelist
added 2026/04/20 12:0 a.m.26 views

CVE-2026-29647

In OpenXiangShan NEMU, insufficient Smstateen permission enforcement allows lower-privileged code to access IMSIC state via stopei/vstopei CSRs even when mstateen0.IMSIC is cleared, potentially enabling cross-context information leakage or disruption of interrupt handling...

0.00034EPSS
Exploits0References3
OSV
OSV
added 2018/01/09 9:29 p.m.0 views

CVE-2018-3610

SEMA driver in Intel Driver and Support Assistant before version 3.1.1 allows a local attacker the ability to read and writing to Memory Status registers potentially allowing information disclosure or a denial of service condition...

6CVSS5.8AI score
Exploits0References1
Prion
Prion
added 2018/01/09 9:29 p.m.10 views

Race condition

SEMA driver in Intel Driver and Support Assistant before version 3.1.1 allows a local attacker the ability to read and writing to Memory Status registers potentially allowing information disclosure or a denial of service condition...

3.6CVSS5.8AI score0.00046EPSS
Exploits0References1Affected Software1
NVD
NVD
added 2018/01/09 9:29 p.m.8 views

CVE-2018-3610

SEMA driver in Intel Driver and Support Assistant before version 3.1.1 allows a local attacker the ability to read and writing to Memory Status registers potentially allowing information disclosure or a denial of service condition...

6CVSS5.9AI score0.00046EPSS
Exploits0References1
Intel
Intel
added 2018/01/09 12:0 a.m.8 views

Intel Driver and Support Assistant Information Disclosure

Summary: SEMA driver in Intel Driver and Support Assistant before version 3.1.1 allows a local attacker with administrative access the ability to read and write to Memory Status Registers potentially allowing for information disclosure or a denial of service condition. Description: SEMA driver in...

6.9AI score
Exploits0
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