CVE-2017-5681

The RSA-CRT implementation in the Intel QuickAssist Technology QAT Engine for OpenSSL versions prior to 0.5.19 may allow remote attackers to obtain private RSA keys by conducting a Lenstra side-channel attack...

CVE-2017-5681

The RSA-CRT implementation in the Intel QuickAssist Technology QAT Engine for OpenSSL versions prior to 0.5.19 may allow remote attackers to obtain private RSA keys by conducting a Lenstra side-channel attack...

CVE-2016-6882

MatrixSSL before 3.8.7, when the DHERSA based cipher suite is supported, makes it easier for remote attackers to obtain RSA private key information by conducting a Lenstra side-channel attack...

CVE-2016-6882

MatrixSSL before 3.8.7, when the DHERSA based cipher suite is supported, makes it easier for remote attackers to obtain RSA private key information by conducting a Lenstra side-channel attack...

Design/Logic Flaw

MatrixSSL before 3.8.7, when the DHERSA based cipher suite is supported, makes it easier for remote attackers to obtain RSA private key information by conducting a Lenstra side-channel attack...

CVE-2016-6882

CVE-2016-6882 concerns MatrixSSL prior to 3.8.7. When DHE_RSA cipher suites are enabled, remote attackers may exploit a Lenstra side-channel to glean RSA private key information. The vulnerability is limited to affected builds of MatrixSSL and is primarily an information-leak risk to private RSA ...

CVE-2015-2877

Kernel Samepage Merging KSM in the Linux kernel 2.6.32 through 4.x does not prevent use of a write-timing side channel, which allows guest OS users to defeat the ASLR protection mechanism on other guest OS instances via a Cross-VM ASL INtrospection CAIN attack. NOTE: the vendor states "Basically ...

CVE-2017-5925

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

Design/Logic Flaw

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

CVE-2017-5926

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

CVE-2017-5927

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

Code injection

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

Code injection

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

CVE-2017-5927

CVE-2017-5927 affects ARM processors where page table walks by the MMU during virtual-to-physical address translation leave traces in the last-level cache. A side-channel attack via JavaScript can infer memory and code pointers, breaking ASLR. The linked SUSE entry and related coverage confirm th...

CVE-2017-5926

CVE-2017-5926 describes a side-channel vulnerability affecting AMD processors where page table walks by the MMU leave traces in the last-level cache. A JavaScript-based attack can leak data and code pointers, effectively breaking ASLR. The connected documents confirm the issue is tied to AMD MMU/...

CVE-2017-5925

CVE-2017-5925 describes an Intel MMU page-table walk side-channel vulnerability where, during virtual-to-physical address translation, the MMU leaves traces in the last-level cache, enabling a JavaScript-based attack to leak data and code pointers and break ASLR. Connected sources note that the A...

CVE-2017-5925

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern Intel processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

CVE-2017-5927

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern ARM processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

CVE-2017-5926

Page table walks conducted by the MMU during virtual to physical address translation leave a trace in the last level cache of modern AMD processors. By performing a side-channel attack on the MMU operations, it is possible to leak data and code pointers from JavaScript, breaking ASLR...

Side-channel Timing Attack

OpenSSL is vulnerable to side-channel timing attacks. These attacks are possible because the Montgomery ladder implementation doesn't run swap operations in constant time which makes it easier for local users to obtain ECDSA nonce values...