riscv-isa-sim

Spike RISC-V ISA Simulator About Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. It is named after the golden spike used to celebrate the completion of the US transcontinental railway. Spike supports the following RISC-V ISA features: RV32I and RV64I ba...

qrv

QRV — a QNX Neutrino-based operating system, re-imagined for 64-bit RISC-V QRV is a ground-up adaptation and re-implementation of the QNX Neutrino 6.4 operating system for modern 64-bit hardware, with RISC-V rv64g as the primary architecture and x86-64 as a secondary target. The project started o...

DeadDialect

DeadDialect Every boot speaks a different language. Yesterday's binary is today's dead code. A session-unique RISC-V ISA remapping system. Every time the system boots, it generates a fresh cryptographic permutation of the instruction set. Binaries compiled for one session are cryptographically...

ckb-vm

Nervos CKB VM About CKB VM CKB VM is a pure software implementation of the RISC-V instruction set used as scripting VM in CKB. Right now it implements full IMCB instructions for both 32-bit and 64-bit register size support. In the future we might also implement V extensions to enable better crypt...

vpod

Vpod Live demo • Getting Started • Documentation • Issues • Contributing What is a vpod ? A vpod is a lightweight, portable sandbox that gives an untrusted process an instant Linux environment. It uses a RISC‑V architecture and runs entirely inside WebAssembly. Fast startup : Boot in under a...

pico2-swd-riscv

pico2-swd-riscv SWD debug probe for RP2350 RISC-V Hazard3 cores. One Pico2 debugs another via two GPIO wires. 0. VIBE CODE WARNING WRITTEN BY HUMAN About 80% of the code is vibe coded; The readme is almost completely generated except the whole vibe-code-warning section. I spent many nights with...

boxlambda

About BoxLambda BoxLambda is a hardware-software crossover project creating a homebrew, retro-style FPGA-based microcomputer. The goal is to create a sandbox environment for experimenting with software and FPGA gateware. The Physical Setup The physical setup. Current Features Target FPGA:...

arduino-pico

Arduino-Pico Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards This is a port of Arduino to the RP2040 Raspberry Pi Pico processor and RP2350 Raspberry Pi Pico 2 processor. It uses the bare Raspberry Pi Pico SDK and a custom GCC 14.3/Newlib 4.5 toolchain and supports ARM and RISC-V...

riscv-isa-sim

Spike RISC-V ISA Simulator Acerca de Spike, el simulador de ISA RISC-V, implementa un modelo funcional de uno o más harts RISC-V. Recibe su nombre del clavo de oro golden spike utilizado para celebrar la finalización del ferrocarril transcontinental de EE. UU. Spike soporta las siguientes...

mojo-v

Mojo-V: Computación Secreta para RISC-V Mojo-V pronunciado “mojo-five” es una nueva extensión de RISC-V que introduce capacidades de programación orientadas a la privacidad para RISC-V. Mojo-V implementa computación secreta, lo que permite una ejecución segura, eficiente y oblivious a los datos s...

mojo-v

Mojo-V: Secret Computation for RISC-V Mojo-V pronounced “mojo-five” is a new RISC-V extension that introduces privacy-oriented programming capabilities for RISC-V. Mojo-V implements secret computation, enabling secure, efficient, and data-oblivious execution without reliance on fragile software a...

CVE-2026-89513

In the Linux kernel, the following vulnerability has been resolved: RISC-V: KVM: Fix PMU event info array size overflow SBI PMU EVENTGETINFO stores guest-controlled numevents sizeofeinfo in a 32-bit integer. On RV64, numevents = 0x10000001 makes 0x100000010 truncate to 16. KVM then allocates one...

sfuzz

SFUZZ Start date: Dec, 2021 This is a coverage-guided, emulation based greybox fuzzer that makes use of a custom Just-In-Time compiler to achieve near-native performance. It works by lifting RISC-V elf binaries to an intermediate representation before JIT compiling them to x86 during execution...

GoTEE

Introduction The GoTEE framework implements concurrent instantiation of TamaGo based unikernels in privileged and unprivileged modes, interacting with each other through monitor mode and custom system calls. With these capabilities GoTEE implements a TamaGo based Trusted Execution Environments TE...

Linux Distros Unpatched Vulnerability : CVE-2026-89513

The Linux/Unix host has one or more packages installed that are impacted by a vulnerability without a vendor supplied patch available. - RISC-V: KVM: Fix PMU event info array size overflow SBI PMU EVENTGETINFO stores guest-controlled numevents sizeofeinfo in a 32-bit integer. On RV64, numevents =...

CVE-2026-89513

A flaw was found in the Linux kernel's KVM Kernel-based Virtual Machine component for RISC-V architectures. A malicious guest operating system could exploit an integer overflow vulnerability by providing a crafted number of Performance Monitoring Unit PMU events during the SBI PMU EVENTGETINFO...

CVE-2026-89513

In the Linux kernel, the following vulnerability has been resolved: RISC-V: KVM: Fix PMU event info array size overflow SBI PMU EVENTGETINFO stores guest-controlled numevents sizeofeinfo in a 32-bit integer. On RV64, numevents = 0x10000001 makes 0x100000010 truncate to 16. KVM then allocates one...

DEBIAN-CVE-2026-89513

In the Linux kernel, the following vulnerability has been resolved: RISC-V: KVM: Fix PMU event info array size overflow SBI PMU EVENTGETINFO stores guest-controlled numevents sizeofeinfo in a 32-bit integer. On RV64, numevents = 0x10000001 makes 0x100000010 truncate to 16. KVM then allocates one...

CVE-2026-89513

CVE-2026-89513 is an integer overflow in the Linux kernel's KVM (RISC-V) component. The SBI PMU EVENT_GET_INFO handler stores num_events * sizeof(*einfo) in a 32-bit integer; on RV64, a guest-supplied num_events = 0x10000001 truncates the allocation to 16 bytes while KVM still loops over the orig...

CVE-2026-89513 RISC-V: KVM: Fix PMU event info array size overflow

In the Linux kernel, the following vulnerability has been resolved: RISC-V: KVM: Fix PMU event info array size overflow SBI PMU EVENTGETINFO stores guest-controlled numevents sizeofeinfo in a 32-bit integer. On RV64, numevents = 0x10000001 makes 0x100000010 truncate to 16. KVM then allocates one...