Reverse-Engineering

A FREE comprehensive reverse engineering tutorial covering x86, x64, 32-bit/64-bit ARM, 8-bit AVR and 32-bit RISC-V architectures. FREE EMBEDDED HACKING COURSE PROMO HERE Join DC540 Discord HERE Today's Tutorial October 25, 2026 Lesson 336: Hacking RISC-V Course Chapter 4: Binary Numbers This...

arduino-pico

Arduino-Pico Raspberry Pi Pico Arduino core, for all RP2040 and RP2350 boards This is a port of Arduino to the RP2040 Raspberry Pi Pico processor and RP2350 Raspberry Pi Pico 2 processor. It uses the bare Raspberry Pi Pico SDK and a custom GCC 16.1/Newlib 4.6 toolchain and supports ARM and RISC-V...

ckb-vm

Nervos CKB VM About CKB VM CKB VM is a pure software implementation of the RISC-V instruction set used as scripting VM in CKB. Right now it implements full IMCB instructions for both 32-bit and 64-bit register size support. In the future we might also implement V extensions to enable better crypt...

hcon2026hwctf

Hardware Hacking CTF hcon2026hwctf If you’re into hardware CTFs, here’s the first public challenge from HC0N CTF 2026 featuring RISC-V RP2350 exploitation challenges low level We’ve tried to make the challenge not too elitist or difficult, so that the hundreds of conference participants have a...

GoTEE-example

Introduction The GoTEE framework implements concurrent instantiation of TamaGo based unikernels in privileged and unprivileged modes, interacting with each other through monitor mode and custom system calls. With these capabilities GoTEE implements a TamaGo based Trusted Execution Environments TE...

boxlambda

About BoxLambda BoxLambda is a hardware-software crossover project creating an experimental, retro-style, FPGA-based microcomputer. The goal is to create a new computer to explore old ideas. The Physical Setup The physical setup. Current Features Target FPGA: Arty-A7-100T. Ibex RISC-V core with...

pico2-swd-riscv

pico2-swd-riscv SWD debug probe for RP2350 RISC-V Hazard3 cores. One Pico2 debugs another via two GPIO wires. 0. VIBE CODE WARNING WRITTEN BY HUMAN About 80% of the code is vibe coded; The readme is almost completely generated except the whole vibe-code-warning section. I spent many nights with...

vpod

Vpod Live demo • Getting Started • Documentation • Issues • Contributing What is a vpod ? A vpod is a lightweight, portable sandbox that gives an untrusted process an instant Linux environment. It uses a RISC‑V architecture and runs entirely inside WebAssembly. Fast startup : Boot in under a...

riscv-isa-sim

Spike RISC-V ISA Simulator About Spike, the RISC-V ISA Simulator, implements a functional model of one or more RISC-V harts. It is named after the golden spike used to celebrate the completion of the US transcontinental railway. Spike supports the following RISC-V ISA features: RV32I and RV64I ba...

GoTEE

Introduction The GoTEE framework implements concurrent instantiation of TamaGo based unikernels in privileged and unprivileged modes, interacting with each other through monitor mode and custom system calls. With these capabilities GoTEE implements a TamaGo based Trusted Execution Environments TE...

mojo-v

Mojo-V: Secret Computation for RISC-V Mojo-V pronounced “mojo-five” is a new RISC-V extension that introduces privacy-oriented programming capabilities for RISC-V. Mojo-V implements secret computation, enabling secure, efficient, and data-oblivious execution without reliance on fragile software a...

DeadDialect

DeadDialect Every boot speaks a different language. Yesterday's binary is today's dead code. A session-unique RISC-V ISA remapping system. Every time the system boots, it generates a fresh cryptographic permutation of the instruction set. Binaries compiled for one session are cryptographically...

riscy-business

riscy-business Article:RISC-Y Business: Raging against the reduced machine. Prerequisites Visual Studio 2022 with the C++ Clang Compiler for Windows 16.0.5 component CMake 3.26 earlier may work, but not recommended riscvm This folder contains the VM host rv64i interpreter. To build: cd riscvm cma...

DASICS-CVE-2021-3156

DASICS CVE-2021-3156 Version Requirements sudo: 1.8.31 glibc: 2.31 Linux: 4.18 or 5.10.167-gee203559bc0b-dirty Usage For convenience, when compiling Linux, do not use the initramfs method. Instead, use the rootfs.img provided in this repository as the root filesystem to boot. It contains the...

qrv

QRV — a QNX Neutrino-based operating system, re-imagined for 64-bit RISC-V QRV is a ground-up adaptation and re-implementation of the QNX Neutrino 6.4 operating system for modern 64-bit hardware, with RISC-V rv64g as the primary architecture and x86-64 as a secondary target. The project started o...

sfuzz

SFUZZ Start date: Dec, 2021 This is a coverage-guided, emulation based greybox fuzzer that makes use of a custom Just-In-Time compiler to achieve near-native performance. It works by lifting RISC-V elf binaries to an intermediate representation before JIT compiling them to x86 during execution...

CLEANSTART-2026-YQ62547 Issue summary: A non-constant-time optimized implementation of scalar point multiplication is used for SM2 private key operations on ARM64 and RISC-V platforms

CVE-2026-54875 affects multiple packages. Issue summary: A non-constant-time optimized implementation of scalar point multiplication is used for SM2 private key operations on ARM64 and RISC-V platforms. See references for individual vulnerability details...

CVE-2026-98639

A flaw was found in the Linux kernel's KVM Kernel-based Virtual Machine subsystem for the RISC-V architecture. During nested virtualization acceleration, control flags are written before the target page parameters are properly committed to shared memory. Consequently, the supervisor interface or...

CVE-2026-93132

A flaw was found in the Linux kernel's Advanced Configuration and Power Interface ACPI implementation for RISC-V architectures. Specifically, the riscvacpiaddprtdep function contains a loop that incorrectly handles error conditions. This can cause the loop to skip necessary entry pointer updates,...

CVE-2026-92518

A flaw was found in the Linux kernel's RISC-V BPF JIT compiler. When Control-Flow Integrity CFI with Clang is enabled, an error in calculating the tail call jump offset can lead to kernel stack corruption. This issue causes the system to improperly adjust the stack pointer, which can result in...