CVE-2025-48507

The security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

EUVD-2025-198576

The security state of the calling processor into Arm® Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

CVE-2025-54515

The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors TF-A for Arm’s Power State Coordination Interface PSCI commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were...

CVE-2025-48507

The security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

CVE-2025-54515

The Secure Flag passed to Versal™ Adaptive SoC’s Trusted Firmware for Cortex®-A processors TF-A for Arm’s Power State Coordination Interface PSCI commands were incorrectly set to secure instead of using the processor’s actual security state. This would allow the PSCI requests to appear they were...

CVE-2025-54515

The CVE describes a mis-set Secure Flag in the Versal Adaptive SoC’s ARM TF-A PSCI handling, where PSCI commands were marked secure instead of reflecting the processor’s actual security state. Affected: Versal Adaptive SoC with Cortex-A TF-A, enabling PSCI requests to appear from the secure state...

CVE-2025-48507

CVE-2025-48507 concerns the unused security state of the calling processor in Arm Trusted Firmware (TF-A) , which could allow a non-secure processor to access secure memories , perform privileged cryptographic operations , and control subsystems within the SOC. Documented exposure stems from AMD-...

CVE-2025-48507

The security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

CVE-2025-48507

The security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

CVE-2025-48507

The security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability to turn on and off subsystems within the SOC...

AMD Zynq UltraScale+ 安全漏洞

AMD Zynq UltraScale+ is a multiprocessor system-on-chip from UltraMicroelectronics AMD. A security vulnerability exists in AMD Zynq UltraScale+ that originates from the unused security state of the calling processor and could result in a non-secure processor accessing secure memory or cryptograph...

AMD Versal Adaptive SoC 安全漏洞

AMD Versal Adaptive SoC is a chip from UltraMicro Semiconductor AMD. A security vulnerability exists in the AMD Versal Adaptive SoC that stems from an improperly set security flag on the PSCI command, which could result in requests from a non-secure state being mistakenly recognized as coming fro...

PT-2025-47853

Name of the Vulnerable Software and Affected Versions Arm® Trusted Firmware TF-A affected versions not specified Description The security state of the calling processor when entering Arm® Trusted Firmware TF-A is not properly utilized. This could allow processors operating in a non-secure state t...

Updated unbound packages fix security vulnerability

Several multi-vendor cache poisoning vulnerabilities have been discovered in caching resolvers for non-DNSSEC protected data. Unbound is vulnerable for some of these cases that could lead to domain hijacking CVE-2025-11411...

Missing Use of the Secure Flag in Zynq™ UltraScale+™ SoC Trusted Firmware

Summary A researcher reported that the security state of the calling processor into Trusted Firmware TF-A is not used and could potentially allow non-secure processors access to secure memories, access to crypto operations, and the ability turn on and off subsystems within the SoC...

CVE-2025-10693

When SmartStart Inclusion fails during the onboarding of a Z-Wave PIR sensor, the sensor will join the network as a non-secure device. This vulnerability exists in Silicon Labs' Z-Wave PIR Sensor Reference design delivered as part of SiSDK v2025.6.0 and v2025.6.1...

EUVD-2025-37394

When SmartStart Inclusion fails during the onboarding of a Z-Wave PIR sensor, the sensor will join the network as a non-secure device. This vulnerability exists in Silicon Labs' Z-Wave PIR Sensor Reference design delivered as part of SiSDK v2025.6.0 and v2025.6.1...

CVE-2025-10693

When SmartStart Inclusion fails during the onboarding of a Z-Wave PIR sensor, the sensor will join the network as a non-secure device. This vulnerability exists in Silicon Labs' Z-Wave PIR Sensor Reference design delivered as part of SiSDK v2025.6.0 and v2025.6.1...

CVE-2025-10693 Silicon Labs Z-Wave PIR Sensor Joins Network as Non-Secure

When SmartStart Inclusion fails during the onboarding of a Z-Wave PIR sensor, the sensor will join the network as a non-secure device. This vulnerability exists in Silicon Labs' Z-Wave PIR Sensor Reference design delivered as part of SiSDK v2025.6.0 and v2025.6.1...

CVE-2025-10693 Silicon Labs Z-Wave PIR Sensor Joins Network as Non-Secure

When SmartStart Inclusion fails during the onboarding of a Z-Wave PIR sensor, the sensor will join the network as a non-secure device. This vulnerability exists in Silicon Labs' Z-Wave PIR Sensor Reference design delivered as part of SiSDK v2025.6.0 and v2025.6.1...