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NVD
NVD
added 2026/04/20 8:16 p.m.0 views

CVE-2026-29649

NEMU contains an implementation flaw in its RISC-V Hypervisor CSR handling where henvcfg7:4 CBIE/CBCFE/CBZE-related fields is incorrectly masked/updated based on menvcfg7:4, so a machine-mode write to menvcfg can implicitly modify the hypervisor's environment configuration. This can lead to...

9.8CVSS0.00026EPSS
Exploits0References4
ATTACKERKB
ATTACKERKB
added 2026/04/20 12:0 a.m.0 views

CVE-2026-29649

NEMU contains an implementation flaw in its RISC-V Hypervisor CSR handling where henvcfg7:4 CBIE/CBCFE/CBZE-related fields is incorrectly masked/updated based on menvcfg7:4, so a machine-mode write to menvcfg can implicitly modify the hypervisor's environment configuration. This can lead to...

5.7AI score0.00026EPSS
Exploits0References5
RedhatCVE
RedhatCVE
added 2025/11/11 12:50 p.m.2 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS7AI score0.00041EPSS
Exploits1References1
EUVD
EUVD
added 2025/11/10 9:30 p.m.1 views

EUVD-2025-50785

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5AI score0.00041EPSS
Exploits1References3
NVD
NVD
added 2025/11/10 8:15 p.m.2 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS0.00041EPSS
Exploits1References2
OSV
OSV
added 2025/11/10 8:15 p.m.1 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.5CVSS5.4AI score
Exploits0References2
CVE
CVE
added 2025/11/10 12:0 a.m.7 views

CVE-2025-63384

CVE-2025-63384 affects RISC-V Rocket-Chip v1.6 and earlier. The SRET instruction fails to downgrade from M-mode to S-mode as dictated by sstatus.SPP, causing a privilege retention vulnerability where execution remains in Machine mode. Impact is described as high confidentiality risk with no repor...

6.5CVSS6.7AI score0.00041EPSS
Exploits1References2Affected Software1
Vulnrichment
Vulnrichment
added 2025/11/10 12:0 a.m.2 views

CVE-2025-63384

A vulnerability was discovered in RISC-V Rocket-Chip v1.6 and before implementation where the SRET Supervisor-mode Exception Return instruction fails to correctly transition the processor's privilege level. Instead of downgrading from Machine-mode M-mode to Supervisor-mode S-mode as specified by...

6.6AI score0.00041EPSS
Exploits1References2
Positive Technologies
Positive Technologies
added 2025/11/10 12:0 a.m.3 views

PT-2025-46191

Name of the Vulnerable Software and Affected Versions RISC-V Rocket-Chip versions 1.6 and earlier Description A flaw exists in the handling of the SRET Supervisor-mode Exception Return instruction within the processor. Instead of correctly transitioning from Machine-mode M-mode to Supervisor-mode...

6.4AI score0.00041EPSS
Exploits1References5
EUVD
EUVD
added 2025/10/03 8:7 p.m.1 views

EUVD-2025-31738

Malicious code in bioql PyPI...

7.5CVSS6.6AI score0.00195EPSS
Exploits1References6
CVE
CVE
added 2025/09/30 12:0 a.m.15 views

CVE-2025-56301

Summary (CVE-2025-56301) — The issue affects Chipsalliance Rocket-Chip, tied to the CSR logic in the commit f517abbf41abb65cea37421d3559f9739efd00a9. The root cause is a flawed interaction between exception handling and the MRET return mechanism, which can trigger faulty trap behavior when an exc...

7.5CVSS6.8AI score0.00195EPSS
Exploits1References5Affected Software1
Positive Technologies
Positive Technologies
added 2025/09/30 12:0 a.m.2 views

PT-2025-39994

Name of the Vulnerable Software and Affected Versions Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 Description An issue exists in the Control and Status Register CSR logic that allows attackers to corrupt exception handling and privilege state transitions. This occurs du...

7.5CVSS6.5AI score0.00195EPSS
Exploits1References10
Cvelist
Cvelist
added 2025/09/30 12:0 a.m.4 views

CVE-2025-56301

An issue was discovered in Chipsalliance Rocket-Chip commit f517abbf41abb65cea37421d3559f9739efd00a9 2025-01-29 allowing attackers to corrupt exception handling and privilege state transitions via a flawed interaction between exception handling and MRET return mechanisms in the CSR logic when an...

0.00195EPSS
Exploits1References5
Citrix
Citrix
added 2024/07/13 12:0 a.m.4 views

Troubleshooting Linux Virtual Machines in XenServer

This article describes about troubleshooting Linux virtual machines in XenServer. Serial console was used to access UNIX server consoles and most of the network devices switches, routes. The simplicity of serial port hardware and its universality make them popular. Serial console apart from...

6.8AI score
Exploits0
OSV
OSV
added 2017/01/23 9:59 p.m.0 views

UBUNTU-CVE-2016-9382

Xen 4.0.x through 4.7.x mishandle x86 task switches to VM86 mode, which allows local 32-bit x86 HVM guest OS users to gain privileges or cause a denial of service guest OS crash by leveraging a guest operating system that uses hardware task switching and allows a new task to start in VM86 mode...

7.8CVSS7.1AI score0.00124EPSS
Exploits0References3
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