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NVD
NVD
•added 2026/08/19 2:17 p.m.•26 views

CVE-2026-50719

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

6.8CVSS0.00147EPSS
SaveExploits0References1
Cvelist
Cvelist
•added 2026/08/19 12:00 a.m.•46 views

CVE-2026-50719

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

0.00147EPSS
SaveExploits0References1
EUVD
EUVD
•added 2026/08/19 12:00 a.m.•21 views

EUVD-2026-62479

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

5.3AI score0.00147EPSS
SaveExploits0References1
Vulnrichment
Vulnrichment
•added 2026/08/19 12:00 a.m.•15 views

CVE-2026-50719

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

5.9AI score0.00147EPSS
SaveExploits0References1
Rapid7 Vulnerability Database (full)
Rapid7 Vulnerability Database (full)
•added 2026/08/19 12:00 a.m.•8 views

CVE-2026-50719: Improper Access Control

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

6.8CVSS6AI score0.00147EPSS
SaveExploits0References4
CVE
CVE
•added 2026/08/19 12:00 a.m.•80 views

CVE-2026-50719

The Ingenic T41 , and likely the T32, T40, and A1 SoCs, are vulnerable in their boot ROMs due to an improper handling of the SPL header init table. The boot ROM parses and executes an attacker-controlled init table before performing secure boot state checks or signature verification. Because the ...

6.8CVSS5.9AI score0.00147EPSS
SaveExploits0References1
Positive Technologies
Positive Technologies
•added 2026/08/19 12:00 a.m.•35 views

PT-2026-78354

Name of the Vulnerable Software and Affected Versions Ingenic T41 affected versions not specified Ingenic T32 affected versions not specified Ingenic T40 affected versions not specified Ingenic A1 affected versions not specified Description Boot ROMs in certain SoC System on Chip components parse...

6.8CVSS6AI score0.00147EPSS
SaveExploits0References5
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