EUVD-2026-62479

The Ingenic T41, and probably also T32, T40, and A1 SoC boot ROMs parse and execute an attacker-controlled init table from the SPL header before checking the secure boot state and before invoking signature verification. The init table parser supports full-address 32-bit write operations, allowing...

CVE-2026-50719

Ingenic T41/T32/T40/A1 SoC boot ROMs execute an attacker-controlled init table from the SPL header before secure boot verification, using 32-bit writes to disable SRAM-resident secure boot state, allowing unsigned boot code. Hardware-validated on T41; ROM analysis confirms behavior on other chips...