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CVE-2026-74276 spi: xilinx: use FIFO occupancy register to determine buffer size

🗓️ 15 Aug 2026 05:57:48Reported by GoogleType 
osv_cve
 osv_cve
🔗 osv.dev👁 38 Views

Xilinx SPI driver miscalculates FIFO size by one, causing RX FIFO overflow and deadlock in IRQ mode.

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16 Oct 2026 10:42Current
6.1Medium risk
Vulners AI Score6.1
EPSS0.00177
38