ID DEBIAN_DLA-2248.NASL Type nessus Reporter This script is Copyright (C) 2020-2021 and is owned by Tenable, Inc. or an Affiliate thereof. Modified 2020-06-17T00:00:00
Description
The following CVE(s) were reported against src:intel-microcode.
CVE-2020-0543
A new domain bypass transient execution attack known as Special
Register Buffer Data Sampling (SRBDS) has been found. This flaw allows
data values from special internal registers to be leaked by an
attacker able to execute code on any core of the CPU. An unprivileged,
local attacker can use this flaw to infer values returned by affected
instructions known to be commonly used during cryptographic operations
that rely on uniqueness, secrecy, or both.
CVE-2020-0548
A flaw was found in Intel processors where a local attacker is able to
gain information about registers used for vector calculations by
observing register states from other processes running on the system.
This results in a race condition where store buffers, which were not
cleared, could be read by another process or a CPU sibling. The
highest threat from this vulnerability is data confidentiality where
an attacker could read arbitrary data as it passes through the
processor.
CVE-2020-0549
A microarchitectural timing flaw was found on some Intel processors. A
corner case exists where data in-flight during the eviction process
can end up in the 'fill buffers' and not properly cleared
by the MDS mitigations. The fill buffer contents (which were expected
to be blank) can be inferred using MDS or TAA style attack methods to
allow a local attacker to infer fill buffer values.
For Debian 8 'Jessie', these problems have been fixed in version
3.20200609.2~deb8u1.
We recommend that you upgrade your intel-microcode packages.
NOTE: Tenable Network Security has extracted the preceding description
block directly from the DLA security advisory. Tenable has attempted
to automatically clean and format it as much as possible without
introducing additional issues.
#%NASL_MIN_LEVEL 70300
#
# (C) Tenable Network Security, Inc.
#
# The descriptive text and package checks in this plugin were
# extracted from Debian Security Advisory DLA-2248-1. The text
# itself is copyright (C) Software in the Public Interest, Inc.
#
include('deprecated_nasl_level.inc');
include('compat.inc');
if (description)
{
script_id(137418);
script_version("1.4");
script_set_attribute(attribute:"plugin_modification_date", value:"2021/01/11");
script_cve_id("CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549");
script_name(english:"Debian DLA-2248-1 : intel-microcode security update");
script_summary(english:"Checks dpkg output for the updated package.");
script_set_attribute(
attribute:"synopsis",
value:"The remote Debian host is missing a security update."
);
script_set_attribute(
attribute:"description",
value:
"The following CVE(s) were reported against src:intel-microcode.
CVE-2020-0543
A new domain bypass transient execution attack known as Special
Register Buffer Data Sampling (SRBDS) has been found. This flaw allows
data values from special internal registers to be leaked by an
attacker able to execute code on any core of the CPU. An unprivileged,
local attacker can use this flaw to infer values returned by affected
instructions known to be commonly used during cryptographic operations
that rely on uniqueness, secrecy, or both.
CVE-2020-0548
A flaw was found in Intel processors where a local attacker is able to
gain information about registers used for vector calculations by
observing register states from other processes running on the system.
This results in a race condition where store buffers, which were not
cleared, could be read by another process or a CPU sibling. The
highest threat from this vulnerability is data confidentiality where
an attacker could read arbitrary data as it passes through the
processor.
CVE-2020-0549
A microarchitectural timing flaw was found on some Intel processors. A
corner case exists where data in-flight during the eviction process
can end up in the 'fill buffers' and not properly cleared
by the MDS mitigations. The fill buffer contents (which were expected
to be blank) can be inferred using MDS or TAA style attack methods to
allow a local attacker to infer fill buffer values.
For Debian 8 'Jessie', these problems have been fixed in version
3.20200609.2~deb8u1.
We recommend that you upgrade your intel-microcode packages.
NOTE: Tenable Network Security has extracted the preceding description
block directly from the DLA security advisory. Tenable has attempted
to automatically clean and format it as much as possible without
introducing additional issues."
);
script_set_attribute(
attribute:"see_also",
value:"https://lists.debian.org/debian-lts-announce/2020/06/msg00019.html"
);
script_set_attribute(
attribute:"see_also",
value:"https://packages.debian.org/source/jessie/intel-microcode"
);
script_set_attribute(
attribute:"solution",
value:"Upgrade the affected intel-microcode package."
);
script_set_cvss_base_vector("CVSS2#AV:L/AC:L/Au:N/C:P/I:N/A:N");
script_set_cvss_temporal_vector("CVSS2#E:U/RL:OF/RC:C");
script_set_cvss3_base_vector("CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N");
script_set_cvss3_temporal_vector("CVSS:3.0/E:U/RL:O/RC:C");
script_set_attribute(attribute:"exploitability_ease", value:"No known exploits are available");
script_set_attribute(attribute:"plugin_type", value:"local");
script_set_attribute(attribute:"cpe", value:"p-cpe:/a:debian:debian_linux:intel-microcode");
script_set_attribute(attribute:"cpe", value:"cpe:/o:debian:debian_linux:8.0");
script_set_attribute(attribute:"vuln_publication_date", value:"2020/01/28");
script_set_attribute(attribute:"patch_publication_date", value:"2020/06/13");
script_set_attribute(attribute:"plugin_publication_date", value:"2020/06/17");
script_set_attribute(attribute:"generated_plugin", value:"current");
script_end_attributes();
script_category(ACT_GATHER_INFO);
script_copyright(english:"This script is Copyright (C) 2020-2021 and is owned by Tenable, Inc. or an Affiliate thereof.");
script_family(english:"Debian Local Security Checks");
script_dependencies("ssh_get_info.nasl");
script_require_keys("Host/local_checks_enabled", "Host/Debian/release", "Host/Debian/dpkg-l");
exit(0);
}
include("audit.inc");
include("debian_package.inc");
if (!get_kb_item("Host/local_checks_enabled")) audit(AUDIT_LOCAL_CHECKS_NOT_ENABLED);
if (!get_kb_item("Host/Debian/release")) audit(AUDIT_OS_NOT, "Debian");
if (!get_kb_item("Host/Debian/dpkg-l")) audit(AUDIT_PACKAGE_LIST_MISSING);
flag = 0;
if (deb_check(release:"8.0", prefix:"intel-microcode", reference:"3.20200609.2~deb8u1")) flag++;
if (flag)
{
if (report_verbosity > 0) security_note(port:0, extra:deb_report_get());
else security_note(0);
exit(0);
}
else audit(AUDIT_HOST_NOT, "affected");
{"id": "DEBIAN_DLA-2248.NASL", "bulletinFamily": "scanner", "title": "Debian DLA-2248-1 : intel-microcode security update", "description": "The following CVE(s) were reported against src:intel-microcode.\n\nCVE-2020-0543\n\nA new domain bypass transient execution attack known as Special\nRegister Buffer Data Sampling (SRBDS) has been found. This flaw allows\ndata values from special internal registers to be leaked by an\nattacker able to execute code on any core of the CPU. An unprivileged,\nlocal attacker can use this flaw to infer values returned by affected\ninstructions known to be commonly used during cryptographic operations\nthat rely on uniqueness, secrecy, or both.\n\nCVE-2020-0548\n\nA flaw was found in Intel processors where a local attacker is able to\ngain information about registers used for vector calculations by\nobserving register states from other processes running on the system.\nThis results in a race condition where store buffers, which were not\ncleared, could be read by another process or a CPU sibling. The\nhighest threat from this vulnerability is data confidentiality where\nan attacker could read arbitrary data as it passes through the\nprocessor.\n\nCVE-2020-0549\n\nA microarchitectural timing flaw was found on some Intel processors. A\ncorner case exists where data in-flight during the eviction process\ncan end up in the 'fill buffers' and not properly cleared\nby the MDS mitigations. The fill buffer contents (which were expected\nto be blank) can be inferred using MDS or TAA style attack methods to\nallow a local attacker to infer fill buffer values.\n\nFor Debian 8 'Jessie', these problems have been fixed in version\n3.20200609.2~deb8u1.\n\nWe recommend that you upgrade your intel-microcode packages.\n\nNOTE: Tenable Network Security has extracted the preceding description\nblock directly from the DLA security advisory. Tenable has attempted\nto automatically clean and format it as much as possible without\nintroducing additional issues.", "published": "2020-06-17T00:00:00", "modified": "2020-06-17T00:00:00", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}, "href": "https://www.tenable.com/plugins/nessus/137418", "reporter": "This script is Copyright (C) 2020-2021 and is owned by Tenable, Inc. or an Affiliate thereof.", "references": ["https://lists.debian.org/debian-lts-announce/2020/06/msg00019.html", "https://packages.debian.org/source/jessie/intel-microcode"], "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "type": "nessus", "lastseen": "2021-01-12T09:42:43", "edition": 5, "viewCount": 5, "enchantments": {"dependencies": {"references": [{"type": "f5", "idList": ["F5:K22206205"]}, {"type": "cve", "idList": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"]}, {"type": "attackerkb", "idList": ["AKB:555EF2E1-269F-4133-8D13-B67EA80F8CC3"]}, {"type": "openvas", "idList": ["OPENVAS:1361412562310878006", "OPENVAS:1361412562310892248", "OPENVAS:1361412562310108812", "OPENVAS:1361412562310883249", "OPENVAS:1361412562310844468", "OPENVAS:1361412562310844463", "OPENVAS:1361412562310877968", "OPENVAS:1361412562310704701", "OPENVAS:1361412562310853200", "OPENVAS:1361412562310883250"]}, {"type": "archlinux", "idList": ["ASA-202006-10"]}, {"type": "redhat", "idList": ["RHSA-2020:2842", "RHSA-2020:2771", "RHSA-2020:2433", "RHSA-2020:2431", "RHSA-2020:2432", "RHSA-2020:2680", "RHSA-2020:2677", "RHSA-2020:2707", "RHSA-2020:2758", "RHSA-2020:2757"]}, {"type": "amazon", "idList": ["ALAS2-2020-1444", "ALAS-2020-1396"]}, {"type": "fedora", "idList": ["FEDORA:1E93431CA0AD", "FEDORA:29E8B30D1A9E", "FEDORA:3C5D13124326", "FEDORA:3A4183118C44", "FEDORA:2AE7F3118C24"]}, {"type": "nessus", "idList": ["REDHAT-RHSA-2020-2842.NASL", "NEWSTART_CGSL_NS-SA-2020-0071_MICROCODE_CTL.NASL", "REDHAT-RHSA-2020-2771.NASL", "REDHAT-RHSA-2020-2431.NASL", "FEDORA_2020-E8835A5F8E.NASL", "ORACLELINUX_ELSA-2020-2431.NASL", "AL2_ALAS-2020-1444.NASL", "SUSE_SU-2020-1595-1.NASL", "SUSE_SU-2020-1601-1.NASL", "SL_20200610_MICROCODE_CTL_ON_SL6_X.NASL"]}, {"type": "debian", "idList": ["DEBIAN:DSA-4701-1:BB3B8", "DEBIAN:DLA-2248-1:806E4"]}, {"type": "suse", "idList": ["OPENSUSE-SU-2020:0791-1", "OPENSUSE-SU-2020:0818-1"]}, {"type": "oraclelinux", "idList": ["ELSA-2020-2432", "ELSA-2020-2433", "ELSA-2020-2431", "ELSA-2020-5722"]}, {"type": "ubuntu", "idList": ["USN-4385-2", "USN-4385-1"]}, {"type": "cloudfoundry", "idList": ["CFOUNDRY:0835B914E665F771DA10821B3BDE2D9F", "CFOUNDRY:A5CCCF4486FE273FEA953C57B224799B"]}, {"type": "centos", "idList": ["CESA-2020:2432", "CESA-2020:2433"]}, {"type": "hp", "idList": ["HP:C06657032"]}, {"type": "threatpost", "idList": ["THREATPOST:7FB07E6C8DF569F394D4B277BFE12285"]}, {"type": "thn", "idList": ["THN:8841D27BD6D8D04E9583E7E0F20898D5", "THN:2CDA9FC212AD7424B67DFBA5344BC5BD"]}, {"type": "lenovo", "idList": ["LENOVO:PS500303-INTEL-PROCESSORS-SIDE-CHANNEL-DATA-LEAKAGE-VULNERABILITIES-NOSID", "LENOVO:PS500303-NOSID"]}, {"type": "freebsd", "idList": ["FBCBA194-AC7D-11EA-8B5E-B42E99A1B9C3"]}, {"type": "ics", "idList": ["ICSA-20-252-07"]}, {"type": "citrix", "idList": ["CTX275165"]}, {"type": "xen", "idList": ["XSA-320"]}], "modified": "2021-01-12T09:42:43", "rev": 2}, "score": {"value": 7.4, "vector": "NONE", "modified": "2021-01-12T09:42:43", "rev": 2}, "vulnersScore": 7.4}, "sourceData": "#%NASL_MIN_LEVEL 70300\n#\n# (C) Tenable Network Security, Inc.\n#\n# The descriptive text and package checks in this plugin were\n# extracted from Debian Security Advisory DLA-2248-1. The text\n# itself is copyright (C) Software in the Public Interest, Inc.\n#\n\ninclude('deprecated_nasl_level.inc');\ninclude('compat.inc');\n\nif (description)\n{\n script_id(137418);\n script_version(\"1.4\");\n script_set_attribute(attribute:\"plugin_modification_date\", value:\"2021/01/11\");\n\n script_cve_id(\"CVE-2020-0543\", \"CVE-2020-0548\", \"CVE-2020-0549\");\n\n script_name(english:\"Debian DLA-2248-1 : intel-microcode security update\");\n script_summary(english:\"Checks dpkg output for the updated package.\");\n\n script_set_attribute(\n attribute:\"synopsis\",\n value:\"The remote Debian host is missing a security update.\"\n );\n script_set_attribute(\n attribute:\"description\",\n value:\n\"The following CVE(s) were reported against src:intel-microcode.\n\nCVE-2020-0543\n\nA new domain bypass transient execution attack known as Special\nRegister Buffer Data Sampling (SRBDS) has been found. This flaw allows\ndata values from special internal registers to be leaked by an\nattacker able to execute code on any core of the CPU. An unprivileged,\nlocal attacker can use this flaw to infer values returned by affected\ninstructions known to be commonly used during cryptographic operations\nthat rely on uniqueness, secrecy, or both.\n\nCVE-2020-0548\n\nA flaw was found in Intel processors where a local attacker is able to\ngain information about registers used for vector calculations by\nobserving register states from other processes running on the system.\nThis results in a race condition where store buffers, which were not\ncleared, could be read by another process or a CPU sibling. The\nhighest threat from this vulnerability is data confidentiality where\nan attacker could read arbitrary data as it passes through the\nprocessor.\n\nCVE-2020-0549\n\nA microarchitectural timing flaw was found on some Intel processors. A\ncorner case exists where data in-flight during the eviction process\ncan end up in the 'fill buffers' and not properly cleared\nby the MDS mitigations. The fill buffer contents (which were expected\nto be blank) can be inferred using MDS or TAA style attack methods to\nallow a local attacker to infer fill buffer values.\n\nFor Debian 8 'Jessie', these problems have been fixed in version\n3.20200609.2~deb8u1.\n\nWe recommend that you upgrade your intel-microcode packages.\n\nNOTE: Tenable Network Security has extracted the preceding description\nblock directly from the DLA security advisory. Tenable has attempted\nto automatically clean and format it as much as possible without\nintroducing additional issues.\"\n );\n script_set_attribute(\n attribute:\"see_also\",\n value:\"https://lists.debian.org/debian-lts-announce/2020/06/msg00019.html\"\n );\n script_set_attribute(\n attribute:\"see_also\",\n value:\"https://packages.debian.org/source/jessie/intel-microcode\"\n );\n script_set_attribute(\n attribute:\"solution\",\n value:\"Upgrade the affected intel-microcode package.\"\n );\n script_set_cvss_base_vector(\"CVSS2#AV:L/AC:L/Au:N/C:P/I:N/A:N\");\n script_set_cvss_temporal_vector(\"CVSS2#E:U/RL:OF/RC:C\");\n script_set_cvss3_base_vector(\"CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N\");\n script_set_cvss3_temporal_vector(\"CVSS:3.0/E:U/RL:O/RC:C\");\n script_set_attribute(attribute:\"exploitability_ease\", value:\"No known exploits are available\");\n\n script_set_attribute(attribute:\"plugin_type\", value:\"local\");\n script_set_attribute(attribute:\"cpe\", value:\"p-cpe:/a:debian:debian_linux:intel-microcode\");\n script_set_attribute(attribute:\"cpe\", value:\"cpe:/o:debian:debian_linux:8.0\");\n\n script_set_attribute(attribute:\"vuln_publication_date\", value:\"2020/01/28\");\n script_set_attribute(attribute:\"patch_publication_date\", value:\"2020/06/13\");\n script_set_attribute(attribute:\"plugin_publication_date\", value:\"2020/06/17\");\n script_set_attribute(attribute:\"generated_plugin\", value:\"current\");\n script_end_attributes();\n\n script_category(ACT_GATHER_INFO);\n script_copyright(english:\"This script is Copyright (C) 2020-2021 and is owned by Tenable, Inc. or an Affiliate thereof.\");\n script_family(english:\"Debian Local Security Checks\");\n\n script_dependencies(\"ssh_get_info.nasl\");\n script_require_keys(\"Host/local_checks_enabled\", \"Host/Debian/release\", \"Host/Debian/dpkg-l\");\n\n exit(0);\n}\n\n\ninclude(\"audit.inc\");\ninclude(\"debian_package.inc\");\n\n\nif (!get_kb_item(\"Host/local_checks_enabled\")) audit(AUDIT_LOCAL_CHECKS_NOT_ENABLED);\nif (!get_kb_item(\"Host/Debian/release\")) audit(AUDIT_OS_NOT, \"Debian\");\nif (!get_kb_item(\"Host/Debian/dpkg-l\")) audit(AUDIT_PACKAGE_LIST_MISSING);\n\n\nflag = 0;\nif (deb_check(release:\"8.0\", prefix:\"intel-microcode\", reference:\"3.20200609.2~deb8u1\")) flag++;\n\nif (flag)\n{\n if (report_verbosity > 0) security_note(port:0, extra:deb_report_get());\n else security_note(0);\n exit(0);\n}\nelse audit(AUDIT_HOST_NOT, \"affected\");\n", "naslFamily": "Debian Local Security Checks", "pluginID": "137418", "cpe": ["cpe:/o:debian:debian_linux:8.0", "p-cpe:/a:debian:debian_linux:intel-microcode"], "cvss3": {"score": 5.5, "vector": "AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N"}, "scheme": null}
{"f5": [{"lastseen": "2020-04-06T22:39:28", "bulletinFamily": "software", "cvelist": ["CVE-2020-0549", "CVE-2020-0548"], "description": "\nF5 Product Development has evaluated the currently supported releases for potential vulnerability, and no F5 products were found to be vulnerable.\n\nNone\n\n * [K51812227: Understanding Security Advisory versioning](<https://support.f5.com/csp/article/K51812227>)\n * [K41942608: Overview of AskF5 Security Advisory articles](<https://support.f5.com/csp/article/K41942608>)\n * [K4602: Overview of the F5 security vulnerability response policy](<https://support.f5.com/csp/article/K4602>)\n * [K9970: Subscribing to email notifications regarding F5 products](<https://support.f5.com/csp/article/K9970>)\n * [K9957: Creating a custom RSS feed to view new and updated documents](<https://support.f5.com/csp/article/K9957>)\n", "edition": 1, "modified": "2020-01-31T18:48:00", "published": "2020-01-31T18:12:00", "id": "F5:K22206205", "href": "https://support.f5.com/csp/article/K22206205", "title": "Intel vulnerabilities CVE-2020-0548 CVE-2020-0549", "type": "f5", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "cve": [{"lastseen": "2021-02-02T07:36:53", "description": "Cleanup errors in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.", "edition": 11, "cvss3": {"exploitabilityScore": 1.8, "cvssV3": {"baseSeverity": "MEDIUM", "confidentialityImpact": "HIGH", "attackComplexity": "LOW", "scope": "UNCHANGED", "attackVector": "LOCAL", "availabilityImpact": "NONE", "integrityImpact": "NONE", "baseScore": 5.5, "privilegesRequired": "LOW", "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N", "userInteraction": "NONE", "version": "3.1"}, "impactScore": 3.6}, "published": "2020-01-28T01:15:00", "title": "CVE-2020-0548", "type": "cve", "cwe": ["CWE-200"], "bulletinFamily": "NVD", "cvss2": {"severity": "LOW", "exploitabilityScore": 3.9, "obtainAllPrivilege": false, "userInteractionRequired": false, "obtainOtherPrivilege": false, "cvssV2": {"accessComplexity": "LOW", "confidentialityImpact": "PARTIAL", "availabilityImpact": "NONE", "integrityImpact": "NONE", "baseScore": 2.1, "vectorString": "AV:L/AC:L/Au:N/C:P/I:N/A:N", "version": "2.0", "accessVector": "LOCAL", "authentication": "NONE"}, "acInsufInfo": false, "impactScore": 2.9, "obtainUserPrivilege": false}, "cvelist": ["CVE-2020-0548"], "modified": "2020-06-26T03:15:00", "cpe": ["cpe:/o:intel:core_i7-8565u_firmware:-", "cpe:/o:intel:core_i3-7120_firmware:-", "cpe:/o:intel:xeon_5220t_firmware:-", "cpe:/o:intel:xeon_w-2125_firmware:-", "cpe:/o:intel:core_i3-7120t_firmware:-", "cpe:/o:intel:core_i5-8400_firmware:-", "cpe:/o:intel:xeon_6146_firmware:-", "cpe:/o:intel:core_i3-8300t_firmware:-", "cpe:/o:intel:pentium_4415u_firmware:-", "cpe:/o:intel:core_i3-7340_firmware:-", "cpe:/o:intel:xeon_w-2133_firmware:-", "cpe:/o:intel:xeon_e-2224g_firmware:-", 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special register read operations in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.", "edition": 16, "cvss3": {"exploitabilityScore": 1.8, "cvssV3": {"baseSeverity": "MEDIUM", "confidentialityImpact": "HIGH", "attackComplexity": "LOW", "scope": "UNCHANGED", "attackVector": "LOCAL", "availabilityImpact": "NONE", "integrityImpact": "NONE", "baseScore": 5.5, "privilegesRequired": "LOW", "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N", "userInteraction": "NONE", "version": "3.1"}, "impactScore": 3.6}, "published": "2020-06-15T14:15:00", "title": "CVE-2020-0543", "type": "cve", "cwe": ["CWE-200"], "bulletinFamily": "NVD", "cvss2": {"severity": "LOW", "exploitabilityScore": 3.9, "obtainAllPrivilege": false, "userInteractionRequired": false, "obtainOtherPrivilege": false, "cvssV2": {"accessComplexity": "LOW", "confidentialityImpact": "PARTIAL", "availabilityImpact": "NONE", "integrityImpact": "NONE", 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"cpe:/h:intel:celeron_1020e:-", "cpe:/h:intel:core_i5-4430s:-", "cpe:/h:intel:xeon_e3-1225_v5:-", "cpe:/h:intel:core_i9-8950hk:-", "cpe:/h:intel:xeon_e3-1585l_v5:-", "cpe:/h:intel:core_i3-8109u:-", "cpe:/h:intel:core_i7-7560u:-", "cpe:/o:canonical:ubuntu_linux:14.04", "cpe:/h:intel:pentium_g5400:-", "cpe:/h:intel:celeron_g1620:-", "cpe:/h:intel:core_i3-8100:-", "cpe:/h:intel:core_i5-3610me:-", "cpe:/h:intel:pentium_g4520t:-", "cpe:/h:intel:core_i3-i3-8100h:-", "cpe:/h:intel:core_i3-4150:-", "cpe:/h:intel:xeon_e-2146g:-"], "id": "CVE-2020-0543", "href": "https://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2020-0543", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}, "cpe23": ["cpe:2.3:h:intel:pentium_b925c:-:*:*:*:*:*:*:*", "cpe:2.3:h:intel:core_i7-4850hq:-:*:*:*:*:*:*:*", "cpe:2.3:h:intel:core_i5-8250u:-:*:*:*:*:*:*:*", "cpe:2.3:h:intel:core_i7-8565u:-:*:*:*:*:*:*:*", "cpe:2.3:h:intel:core_i5-6500te:-:*:*:*:*:*:*:*", "cpe:2.3:h:intel:core_i3-3210:-:*:*:*:*:*:*:*", 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This flaw\nallows data values from special internal registers to be leaked\nby an attacker able to execute code on any core of the CPU. An\nunprivileged, local attacker can use this flaw to infer values\nreturned by affected instructions known to be commonly used\nduring cryptographic operations that rely on uniqueness, secrecy,\nor both.\n\nCVE-2020-0548\n\nA flaw was found in Intel processors where a local attacker is\nable to gain information about registers used for vector\ncalculations by observing register states from other processes\nrunning on the system. This results in a race condition where\nstore buffers, which were not cleared, could be read by another\nprocess or a CPU sibling. The highest threat from this\nvulnerability is data confidentiality where an attacker could\nread arbitrary data as it passes through the processor.\n\nCVE-2020-0549\n\nA microarchitectural timing flaw was found on some Intel\nprocessors. A corner case exists where data in-flight during the\neviction process can end up in the 'fill buffers' and not properly\ncleared by the MDS mitigations. The fill buffer contents (which\nwere expected to be blank) can be inferred using MDS or TAA style\nattack methods to allow a local attacker to infer fill buffer\nvalues.\");\n\n script_tag(name:\"affected\", value:\"'intel-microcode' package(s) on Debian Linux.\");\n\n script_tag(name:\"solution\", value:\"For Debian 8 'Jessie', these problems have been fixed in version\n3.20200609.2~deb8u1.\n\nWe recommend that you upgrade your intel-microcode packages.\");\n\n script_tag(name:\"solution_type\", value:\"VendorFix\");\n script_tag(name:\"qod_type\", value:\"package\");\n\n exit(0);\n}\n\ninclude(\"revisions-lib.inc\");\ninclude(\"pkg-lib-deb.inc\");\n\nres = \"\";\nreport = \"\";\nif(!isnull(res = isdpkgvuln(pkg:\"intel-microcode\", ver:\"3.20200609.2~deb8u1\", rls:\"DEB8\"))) {\n report += res;\n}\n\nif(report != \"\") {\n security_message(data:report);\n} else if(__pkg_match) {\n exit(99);\n}\n\nexit(0);\n", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "redhat": [{"lastseen": "2020-06-30T13:53:52", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.", "modified": "2020-06-30T15:52:02", "published": "2020-06-30T15:41:47", "id": "RHSA-2020:2771", "href": "https://access.redhat.com/errata/RHSA-2020:2771", "type": "redhat", "title": "(RHSA-2020:2771) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-23T13:52:49", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL to point to the GitHub repository since the microcode download.\n section at Intel Download Center does not exist anymore.\n* Avoid temporary file creation, used for here-documents in check_caveats.", "modified": "2020-06-23T16:52:09", "published": "2020-06-23T16:36:30", "id": "RHSA-2020:2677", "href": "https://access.redhat.com/errata/RHSA-2020:2677", "type": "redhat", "title": "(RHSA-2020:2677) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-29T07:55:45", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.", "modified": "2020-06-29T11:45:51", "published": "2020-06-29T11:37:56", "id": "RHSA-2020:2758", "href": "https://access.redhat.com/errata/RHSA-2020:2758", "type": "redhat", "title": "(RHSA-2020:2758) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-23T13:52:31", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.", "modified": "2020-06-23T17:39:41", "published": "2020-06-23T17:33:56", "id": "RHSA-2020:2680", "href": "https://access.redhat.com/errata/RHSA-2020:2680", "type": "redhat", "title": "(RHSA-2020:2680) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-29T07:53:21", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fixes:\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Addition of 06-4d-08/0x01 (AVN B0/C0) microcode at revision 0x12d;\n - Addition of 06-55-06/0xbf (CLX-SP B0) microcode at revision 0x4002f01;\n - Addition of 06-7a-08/0x01 (GLK R0) microcode at revision 0x16;\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode\n (in intel-06-2d-07/intel-ucode/06-2d-07) from revision 0x718 up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd4\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000150\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000064\n up to 0x2006906;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002b\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd4\n up to 0xdc;\n - Update of 06-7a-01/0x01 (GLK B0) microcode from revision 0x2e up to 0x32;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xc6\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xc6\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xc6\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xc6\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xc6 up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xc6 up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xc6\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xc6 up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xae\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xc6 up to 0xd6.\n - Update of 06-a6-00/0x80 (CML-U 6+2 A0) from revision 0xc6 up to 0xca.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Add 06-55-04 (SKL-X/W) caveat, enable it by default.\n* Update stale posttrans dependency, add triggers for proper handling\n of the debug kernel flavour along with kernel-rt.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL to point to the GitHub repository since the microcode download\n section at Intel Download Center does not exist anymore.\n* Avoid temporary file creation, used for here-documents in check_caveats.", "modified": "2020-06-29T11:41:58", "published": "2020-06-29T11:37:51", "id": "RHSA-2020:2757", "href": "https://access.redhat.com/errata/RHSA-2020:2757", "type": "redhat", "title": "(RHSA-2020:2757) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-11T15:53:29", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200602 release, addresses:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n- Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.\n\n* Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models.\n\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n\n* Update stale posttrans dependency, add triggers for proper handling\n of the debug kernel flavour along with kernel-rt.", "modified": "2020-06-11T18:46:20", "published": "2020-06-09T22:20:28", "id": "RHSA-2020:2432", "href": "https://access.redhat.com/errata/RHSA-2020:2432", "type": "redhat", "title": "(RHSA-2020:2432) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-23T15:53:23", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n* Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.", "modified": "2020-06-23T19:25:52", "published": "2020-06-23T19:21:25", "id": "RHSA-2020:2707", "href": "https://access.redhat.com/errata/RHSA-2020:2707", "type": "redhat", "title": "(RHSA-2020:2707) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-09T19:50:59", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "The microcode_ctl packages provide microcode updates for Intel and AMD processors.\n\nSecurity Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.\n\nBug Fix(es) and Enhancement(s):\n\n* Update Intel CPU microcode to microcode-20200602 release, addresses:\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n\n* Update Intel CPU microcode to microcode-20200520 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78.\n\n(BZ#1839193)\n\n* Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models. (BZ#1835555)", "modified": "2020-06-09T22:47:53", "published": "2020-06-09T22:27:54", "id": "RHSA-2020:2433", "href": "https://access.redhat.com/errata/RHSA-2020:2433", "type": "redhat", "title": "(RHSA-2020:2433) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-23T15:55:47", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n* Do not update 06-4e-03 (SKL-U/Y) and 06-5e-03 (SKL-H/S/Xeon E3 v5) to revision\n 0xdc, use 0xd6 by default.\n* Enable 06-2d-07 (SNB-E/EN/EP) caveat by default.\n* Enable 06-55-04 (SKL-SP/X/W) caveat by default.", "modified": "2020-06-23T19:25:47", "published": "2020-06-23T19:21:07", "id": "RHSA-2020:2706", "href": "https://access.redhat.com/errata/RHSA-2020:2706", "type": "redhat", "title": "(RHSA-2020:2706) Moderate: microcode_ctl security, bug fix and enhancement update", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-23T13:55:01", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Security Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS\nscore, acknowledgments, and other related information, refer to the CVE page(s)\nlisted in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200609 release:\n - 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revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n- Change the URL to point to the GitHub repository since the microcode download\n section at Intel Download Center does not exist anymore.\n[4:20191115-4.20191115.6]\n- Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models.\n[4:20191115-4.20191115.5]\n- Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.", "edition": 1, "modified": "2020-06-10T00:00:00", "published": "2020-06-10T00:00:00", "id": "ELSA-2020-2431", "href": "http://linux.oracle.com/errata/ELSA-2020-2431.html", "title": "microcode_ctl security, bug fix and enhancement update", "type": "oraclelinux", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-19T07:27:35", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "[3:1.17-33.26.0.1]\n- update 06-2d-07 to 0x71a\n- update 06-55-04 to 0x2006906\n- update 06-55-07 to 0x5002f01\n- merge Oracle changes for early load via dracut\n- enable late load on install for UEK4 kernels marked safe (except BDW-79)\n- set early_microcode='no' in virtualized guests to avoid early load bugs [Orabug: 30618737]\n[2:1.17-33.26]\n- Update Intel CPU microcode to microcode-20200602 release, addresses\n CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (#1795353, #1795357, #1827186):\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, 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to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n[2:1.17-33.25]\n- Update Intel CPU microcode to microcode-20200520 release (#1839193):\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78.\n[2:1.17-33.24]\n- Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models (#1835555).\n[2:1.17-33.23]\n- Do not update 06-55-04 (SKL-SP/W/X) to revision 0x2000065, use 0x2000064\n by default (#1774635).\n[2:1.17-33.22]\n- Update Intel CPU microcode to microcode-20191115 release:\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) from revision 0xd4 up to 0xd6;\n - Update of 06-5e-03/0x36 (SKL-H/S/Xeon E3 R0/N0) from revision 0xd4\n up to 0xd6;\n - Update of 06-8e-09/0x10 (AML-Y 2+2 H0) from revision 0xc6 up to 0xca;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) from revision 0xc6 up to 0xca;\n - Update of 06-8e-0a/0xc0 (CFL-U 4+3e D0) from revision 0xc6 up to 0xca;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) from revision 0xc6 up to 0xca;\n - Update of 06-8e-0c/0x94 (AML-Y V0, CML-U 4+2 V0, WHL-U V0) from revision\n 0xc6 up to 0xca;\n - Update of 06-9e-09/0x2a (KBL-G/X H0, KBL-H/S/Xeon E3 B0) from revision 0xc6\n up to 0xca;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E U0) from revision 0xc6 up to 0xca;\n - Update of 06-9e-0b/0x02 (CFL-S B0) from revision 0xc6 up to 0xca;\n - Update of 06-9e-0c/0x22 (CFL-S/Xeon E P0) from revision 0xc6 up to 0xca;\n - Update of 06-9e-0d/0x22 (CFL-H/S R0) from revision 0xc6 up to 0xca;\n - Update of 06-a6-00/0x80 (CML-U 6+2 A0) from revision 0xc6 up to 0xca.\n[2:1.17-33.21]\n- Update Intel CPU microcode to microcode-20191113 release:\n - Update of 06-9e-0c (CFL-H/S P0) microcode from revision 0xae up to 0xc6.\n- Drop 0001-releasenote-changes-summary-fixes.patch.\n[2:1.17-33.20]\n- Package the publicy available microcode-20191112 release (#1755021):\n - Addition of 06-4d-08/0x1 (AVN B0/C0) microcode at revision 0x12d;\n - Addition of 06-55-06/0xbf (CSL-SP B0) microcode at revision 0x400002c;\n - Addition of 06-7a-08/0x1 (GLK R0) microcode at revision 0x16;\n - Update of 06-55-03/0x97 (SKL-SP B1) microcode from revision 0x1000150\n up to 0x1000151;\n - Update of 06-55-04/0xb7 (SKL-SP H0/M0/U0, SKL-D M1) microcode from revision\n 0x2000064 up to 0x2000065;\n - Update of 06-55-07/0xbf (CSL-SP B1) microcode from revision 0x500002b\n up to 0x500002c;\n - Update of 06-7a-01/0x1 (GLK B0) microcode from revision 0x2e up to 0x32;\n- Include 06-9e-0c (CFL-H/S P0) microcode from the microcode-20190918 release.\n- Correct the releasenote file (0001-releasenote-changes-summary-fixes.patch).\n- Update README.caveats with the link to the new Knowledge Base article.", "edition": 1, "modified": "2020-06-18T00:00:00", "published": "2020-06-18T00:00:00", "id": "ELSA-2020-2433", "href": "http://linux.oracle.com/errata/ELSA-2020-2433.html", "title": "microcode_ctl security, bug fix and enhancement update", "type": "oraclelinux", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-19T03:29:48", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "[2:2.1-61.6.0.1]\n- update 06-2d-07 to 0x71a\n- update 06-55-04 to 0x2006906\n- update 06-55-07 to 0x5002f01\n- for Intel, do not trigger load if on-disk microcode is not an update [Orabug: 30634727]\n- set early_microcode='no' in virtualized guests to avoid early load bugs [Orabug: 30618736]\n- do not late load prior to 3.10.0\n- ensure late loading fixes are present on 4.1.12-* and 4.14.35-*\n- enable early and late load for 5.4.17-*\n- enable early loading for 06-4f-01\n[2:2.1-61.6]\n- Avoid temporary file creation, used for here-documents in check_caveats.\n[2:2.1-61.5]\n- Update Intel CPU microcode to microcode-20200602 release, addresses\n CVE-2020-0543, CVE-2020-0548, CVE-2020-0549 (#1827189):\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 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handling\n of the debug kernel flavour along with kernel-rt.", "edition": 1, "modified": "2020-06-18T00:00:00", "published": "2020-06-18T00:00:00", "id": "ELSA-2020-2432", "href": "http://linux.oracle.com/errata/ELSA-2020-2432.html", "title": "microcode_ctl security, bug fix and enhancement update", "type": "oraclelinux", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-25T11:34:12", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "[4.1.12-124.39.5.1] \n- x86/speculation: Add Ivy Bridge to affected list (Josh Poimboeuf) [Orabug: 31352782] {CVE-2020-0543}\n- x86/speculation: Add SRBDS vulnerability and mitigation documentation (Mark Gross) [Orabug: 31352782] {CVE-2020-054\n3}\n- x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation (Mark Gross) [Orabug: 31352782] {CVE-\n2020-0543}\n- x86/cpu: Add 'table' argument to cpu_matches() (Mark Gross) [Orabug: 31352782] {CVE-2020-0543}\n- x86/cpu: Add a steppings field to struct x86_cpu_id (Mark Gross) [Orabug: 31352782] {CVE-2020-0543} \n- x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping (Jia Zhang) [Orabug: 31352782] {CVE-2020-0543}", "edition": 2, "modified": "2020-06-10T00:00:00", "published": "2020-06-10T00:00:00", "id": "ELSA-2020-5722", "href": "http://linux.oracle.com/errata/ELSA-2020-5722.html", "title": "Unbreakable Enterprise kernel security update", "type": "oraclelinux", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-25T11:33:44", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "[4.14.35-1902.303.5.3] \n- rds: Deregister all FRWR mr with free_mr (Hans Westgaard Ry) [Orabug: 31476202]\n- Revert rds: Do not cancel RDMAs that have been posted to the HCA (Gerd Rausch) [Orabug: 31475329]\n- Revert rds: Introduce rds_conn_to_path helper (Gerd Rausch) [Orabug: 31475329]\n- Revert rds: Three cancel fixes (Gerd Rausch) [Orabug: 31475318]\n[4.14.35-1902.303.5.2] \n- rds: Three cancel fixes (Hakon Bugge) [Orabug: 31463014]\n[4.14.35-1902.303.5.1] \n- x86/speculation: Add SRBDS vulnerability and mitigation documentation (Mark Gross) [Orabug: 31446720] {CVE-2020-0543} \n- x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation (Mark Gross) [Orabug: 31446720] {CVE-2020-0543} \n- x86/cpu: Add 'table' argument to cpu_matches() (Mark Gross) [Orabug: 31446720] {CVE-2020-0543}\n- x86/cpu: Add a steppings field to struct x86_cpu_id (Mark Gross) [Orabug: 31446720] {CVE-2020-0543}\n[4.14.35-1902.303.5] \n- net/mlx5: Decrease default mr cache size (Artemy Kovalyov) [Orabug: 31446379]", "edition": 3, "modified": "2020-06-18T00:00:00", "published": "2020-06-18T00:00:00", "id": "ELSA-2020-5732", "href": "http://linux.oracle.com/errata/ELSA-2020-5732.html", "title": "Unbreakable Enterprise kernel security update", "type": "oraclelinux", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "ubuntu": [{"lastseen": "2020-07-02T11:40:26", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "USN-4385-1 provided updated Intel Processor Microcode. Unfortunately, \nthat update prevented certain processors in the Intel Skylake family \n(06_4EH) from booting successfully. Additonally, on Ubuntu 20.04 \nLTS, late loading of microcode was enabled, which could lead to \nsystem instability. This update reverts the microcode update for \nthe Skylake processor family and disables the late loading option on \nUbuntu 20.04 LTS.\n\nPlease note that the 'dis_ucode_ldr' kernel command line option can be \nadded in the boot menu to disable microcode loading for system recovery.\n\nWe apologize for the inconvenience.\n\nOriginal advisory details:\n\nIt was discovered that memory contents previously stored in \nmicroarchitectural special registers after RDRAND, RDSEED, and SGX EGETKEY \nread operations on Intel client and Xeon E3 processors may be briefly \nexposed to processes on the same or different processor cores. A local \nattacker could use this to expose sensitive information. (CVE-2020-0543)\n\nIt was discovered that on some Intel processors, partial data values \npreviously read from a vector register on a physical core may be propagated \ninto unused portions of the store buffer. A local attacker could possible \nuse this to expose sensitive information. (CVE-2020-0548)\n\nIt was discovered that on some Intel processors, data from the most \nrecently evicted modified L1 data cache (L1D) line may be propagated into \nan unused (invalid) L1D fill buffer. A local attacker could possibly use \nthis to expose sensitive information. (CVE-2020-0549)", "edition": 2, "modified": "2020-06-10T00:00:00", "published": "2020-06-10T00:00:00", "id": "USN-4385-2", "href": "https://ubuntu.com/security/notices/USN-4385-2", "title": "Intel Microcode regression", "type": "ubuntu", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-07-02T11:37:55", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "It was discovered that memory contents previously stored in \nmicroarchitectural special registers after RDRAND, RDSEED, and SGX EGETKEY \nread operations on Intel client and Xeon E3 processors may be briefly \nexposed to processes on the same or different processor cores. A local \nattacker could use this to expose sensitive information. (CVE-2020-0543)\n\nIt was discovered that on some Intel processors, partial data values \npreviously read from a vector register on a physical core may be propagated \ninto unused portions of the store buffer. A local attacker could possible \nuse this to expose sensitive information. (CVE-2020-0548)\n\nIt was discovered that on some Intel processors, data from the most \nrecently evicted modified L1 data cache (L1D) line may be propagated into \nan unused (invalid) L1D fill buffer. A local attacker could possibly use \nthis to expose sensitive information. (CVE-2020-0549)", "edition": 2, "modified": "2020-06-09T00:00:00", "published": "2020-06-09T00:00:00", "id": "USN-4385-1", "href": "https://ubuntu.com/security/notices/USN-4385-1", "title": "Intel Microcode vulnerabilities", "type": "ubuntu", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "amazon": [{"lastseen": "2020-11-10T12:37:13", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "**Issue Overview:**\n\nA new domain bypass transient execution attack known as Special Register Buffer Data Sampling (SRBDS) has been found. This flaw allows data values from special internal registers to be leaked by an attacker able to execute code on any core of the CPU. An unprivileged, local attacker can use this flaw to infer values returned by affected instructions known to be commonly used during cryptographic operations that rely on uniqueness, secrecy, or both. ([CVE-2020-0543 __](<https://access.redhat.com/security/cve/CVE-2020-0543>))\n\nIncomplete cleanup from specific special register read operations in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. ([CVE-2020-0548 __](<https://access.redhat.com/security/cve/CVE-2020-0548>))\n\nCleanup errors in some data cache evictions for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. ([CVE-2020-0549 __](<https://access.redhat.com/security/cve/CVE-2020-0549>))\n\n \n**Affected Packages:** \n\n\nmicrocode_ctl\n\n \n**Issue Correction:** \nRun _yum update microcode_ctl_ to update your system. \n\n\n \n\n\n**New Packages:**\n \n \n i686: \n microcode_ctl-2.1-47.amzn2.0.7.i686 \n microcode_ctl-debuginfo-2.1-47.amzn2.0.7.i686 \n \n src: \n microcode_ctl-2.1-47.amzn2.0.7.src \n \n x86_64: \n microcode_ctl-2.1-47.amzn2.0.7.x86_64 \n microcode_ctl-debuginfo-2.1-47.amzn2.0.7.x86_64 \n \n \n", "edition": 1, "modified": "2020-06-26T22:53:00", "published": "2020-06-26T22:53:00", "id": "ALAS2-2020-1444", "href": "https://alas.aws.amazon.com/AL2/ALAS-2020-1444.html", "title": "Medium: microcode_ctl", "type": "amazon", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-11-10T12:37:01", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "**Issue Overview:**\n\nA new domain bypass transient execution attack known as Special Register Buffer Data Sampling (SRBDS) has been found. This flaw allows data values from special internal registers to be leaked by an attacker able to execute code on any core of the CPU. An unprivileged, local attacker can use this flaw to infer values returned by affected instructions known to be commonly used during cryptographic operations that rely on uniqueness, secrecy, or both. Incomplete cleanup from specific special register read operations in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. ([CVE-2020-0543 __](<https://access.redhat.com/security/cve/CVE-2020-0543>))\n\nCleanup errors in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. ([CVE-2020-0548 __](<https://access.redhat.com/security/cve/CVE-2020-0548>))\n\nCleanup errors in some data cache evictions for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access. ([CVE-2020-0549 __](<https://access.redhat.com/security/cve/CVE-2020-0549>))\n\n \n**Affected Packages:** \n\n\nmicrocode_ctl\n\n \n**Issue Correction:** \nRun _yum update microcode_ctl_ to update your system. \n\n\n \n\n\n**New Packages:**\n \n \n i686: \n microcode_ctl-2.1-47.39.amzn1.i686 \n microcode_ctl-debuginfo-2.1-47.39.amzn1.i686 \n \n src: \n microcode_ctl-2.1-47.39.amzn1.src \n \n x86_64: \n microcode_ctl-debuginfo-2.1-47.39.amzn1.x86_64 \n microcode_ctl-2.1-47.39.amzn1.x86_64 \n \n \n", "edition": 3, "modified": "2020-07-14T01:55:00", "published": "2020-07-14T01:55:00", "id": "ALAS-2020-1396", "href": "https://alas.aws.amazon.com/ALAS-2020-1396.html", "title": "Medium: microcode_ctl", "type": "amazon", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "fedora": [{"lastseen": "2020-12-21T08:17:56", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "The microcode_ctl utility is a companion to the microcode driver written by Tigran Aivazian <tigran(a)aivazian.fsnet.co.uk>. The microcode update is volatile and needs to be uploaded on each system boot i.e. it doesn't reflash your cpu permanently, reboot and it reverts back to the old microcode. ", "modified": "2020-06-19T01:05:57", "published": "2020-06-19T01:05:57", "id": "FEDORA:1E93431CA0AD", "href": "", "type": "fedora", "title": "[SECURITY] Fedora 32 Update: microcode_ctl-2.1-39.fc32", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-12-21T08:17:56", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "The microcode_ctl utility is a companion to the microcode driver written by Tigran Aivazian <tigran(a)aivazian.fsnet.co.uk>. The microcode update is volatile and needs to be uploaded on each system boot i.e. it doesn't reflash your cpu permanently, reboot and it reverts back to the old microcode. ", "modified": "2020-06-26T01:08:34", "published": "2020-06-26T01:08:34", "id": "FEDORA:29E8B30D1A9E", "href": "", "type": "fedora", "title": "[SECURITY] Fedora 31 Update: microcode_ctl-2.1-39.fc31", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-12-21T08:17:56", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "Kernel-headers includes the C header files that specify the interface between the Linux kernel and userspace libraries and programs. The header files define structures and constants that are needed for building most standard programs and are also needed for rebuilding the glibc package. ", "modified": "2020-06-18T01:02:02", "published": "2020-06-18T01:02:02", "id": "FEDORA:2AE7F3118C24", "href": "", "type": "fedora", "title": "[SECURITY] Fedora 31 Update: kernel-headers-5.6.18-200.fc31", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-12-21T08:17:56", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "Kernel-headers includes the C header files that specify the interface between the Linux kernel and userspace libraries and programs. The header files define structures and constants that are needed for building most standard programs and are also needed for rebuilding the glibc package. ", "modified": "2020-06-15T01:58:35", "published": "2020-06-15T01:58:35", "id": "FEDORA:3C5D13124326", "href": "", "type": "fedora", "title": "[SECURITY] Fedora 32 Update: kernel-headers-5.6.18-300.fc32", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "cloudfoundry": [{"lastseen": "2020-06-22T21:27:07", "bulletinFamily": "software", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "# \n\n## Severity\n\nMedium\n\n## Vendor\n\nCanonical Ubuntu\n\n## Versions Affected\n\n * Canonical Ubuntu 14.04\n * Canonical Ubuntu 16.04\n\n## Description\n\nUSN-4385-1 provided updated Intel Processor Microcode. Unfortunately, that update prevented certain processors in the Intel Skylake family (06_4EH) from booting successfully. Additonally, on Ubuntu 20.04 LTS, late loading of microcode was enabled, which could lead to system instability. This update reverts the microcode update for the Skylake processor family and disables the late loading option on Ubuntu 20.04 LTS.\n\nPlease note that the \u2018dis_ucode_ldr\u2019 kernel command line option can be added in the boot menu to disable microcode loading for system recovery.\n\nWe apologize for the inconvenience.\n\nOriginal advisory details:\n\nIt was discovered that memory contents previously stored in microarchitectural special registers after RDRAND, RDSEED, and SGX EGETKEY read operations on Intel client and Xeon E3 processors may be briefly exposed to processes on the same or different processor cores. A local attacker could use this to expose sensitive information. (CVE-2020-0543)\n\nIt was discovered that on some Intel processors, partial data values previously read from a vector register on a physical core may be propagated into unused portions of the store buffer. A local attacker could possible use this to expose sensitive information. (CVE-2020-0548)\n\nIt was discovered that on some Intel processors, data from the most recently evicted modified L1 data cache (L1D) line may be propagated into an unused (invalid) L1D fill buffer. A local attacker could possibly use this to expose sensitive information. (CVE-2020-0549)\n\nCVEs contained in this USN include: CVE-2020-0543, CVE-2020-0548, CVE-2020-0549.\n\n## Affected Cloud Foundry Products and Versions\n\n_Severity is medium unless otherwise noted._\n\n * Xenial Stemcells \n * 170.x versions prior to 170.221\n * 250.x versions prior to 250.200\n * 315.x versions prior to 315.185\n * 456.x versions prior to 456.114\n * 621.x versions prior to 621.76\n * All other stemcells not listed.\n\n## Mitigation\n\nUsers of affected products are strongly encouraged to follow the mitigations below. The Cloud Foundry project recommends upgrading the following releases:\n\n * Xenial Stemcells \n * Upgrade 170.x versions to 170.221 or greater\n * Upgrade 250.x versions to 250.200 or greater\n * Upgrade 315.x versions to 315.185 or greater\n * Upgrade 456.x versions to 456.114 or greater\n * Upgrade 621.x versions to 621.76 or greater\n * All other stemcells should be upgraded to the latest version available on [bosh.io](<https://bosh.io/stemcells>).\n\n## References\n\n * [USN Notice](<https://usn.ubuntu.com/4385-2/>)\n * [CVE-2020-0543](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0543>)\n * [CVE-2020-0548](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0548>)\n * [CVE-2020-0549](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0549>)\n\n## History\n\n2020-06-10: Initial vulnerability report published.\n", "edition": 1, "modified": "2020-06-22T00:00:00", "published": "2020-06-22T00:00:00", "id": "CFOUNDRY:0835B914E665F771DA10821B3BDE2D9F", "href": "https://www.cloudfoundry.org/blog/usn-4385-2/", "title": "USN-4385-2: Intel Microcode regression | Cloud Foundry", "type": "cloudfoundry", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-22T21:25:33", "bulletinFamily": "software", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "# \n\n## Severity\n\nMedium\n\n## Vendor\n\nCanonical Ubuntu\n\n## Versions Affected\n\n * Canonical Ubuntu 14.04\n * Canonical Ubuntu 16.04\n\n## Description\n\nIt was discovered that memory contents previously stored in microarchitectural special registers after RDRAND, RDSEED, and SGX EGETKEY read operations on Intel client and Xeon E3 processors may be briefly exposed to processes on the same or different processor cores. A local attacker could use this to expose sensitive information. (CVE-2020-0543)\n\nIt was discovered that on some Intel processors, partial data values previously read from a vector register on a physical core may be propagated into unused portions of the store buffer. A local attacker could possible use this to expose sensitive information. (CVE-2020-0548)\n\nIt was discovered that on some Intel processors, data from the most recently evicted modified L1 data cache (L1D) line may be propagated into an unused (invalid) L1D fill buffer. A local attacker could possibly use this to expose sensitive information. (CVE-2020-0549)\n\nCVEs contained in this USN include: CVE-2020-0543, CVE-2020-0548, CVE-2020-0549.\n\n## Affected Cloud Foundry Products and Versions\n\n_Severity is medium unless otherwise noted._\n\n * Xenial Stemcells \n * 170.x versions prior to 170.221\n * 250.x versions prior to 250.200\n * 315.x versions prior to 315.185\n * 456.x versions prior to 456.114\n * 621.x versions prior to 621.76\n * All other stemcells not listed.\n\n## Mitigation\n\nUsers of affected products are strongly encouraged to follow the mitigations below. The Cloud Foundry project recommends upgrading the following releases:\n\n * Xenial Stemcells \n * Upgrade 170.x versions to 170.221 or greater\n * Upgrade 250.x versions to 250.200 or greater\n * Upgrade 315.x versions to 315.185 or greater\n * Upgrade 456.x versions to 456.114 or greater\n * Upgrade 621.x versions to 621.76 or greater\n * All other stemcells should be upgraded to the latest version available on [bosh.io](<https://bosh.io/stemcells>).\n\n## References\n\n * [USN Notice](<https://usn.ubuntu.com/4385-1/>)\n * [CVE-2020-0543](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0543>)\n * [CVE-2020-0548](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0548>)\n * [CVE-2020-0549](<https://people.canonical.com/~ubuntu-security/cve/CVE-2020-0549>)\n\n## History\n\n2020-06-09: Initial vulnerability report published.\n", "edition": 1, "modified": "2020-06-22T00:00:00", "published": "2020-06-22T00:00:00", "id": "CFOUNDRY:A5CCCF4486FE273FEA953C57B224799B", "href": "https://www.cloudfoundry.org/blog/usn-4385-1/", "title": "USN-4385-1: Intel Microcode vulnerabilities | Cloud Foundry", "type": "cloudfoundry", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "debian": [{"lastseen": "2020-06-12T00:58:47", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "- -------------------------------------------------------------------------\nDebian Security Advisory DSA-4701-1 security@debian.org\nhttps://www.debian.org/security/ Salvatore Bonaccorso\nJune 11, 2020 https://www.debian.org/security/faq\n- -------------------------------------------------------------------------\n\nPackage : intel-microcode\nCVE ID : CVE-2020-0543 CVE-2020-0548 CVE-2020-0549\n\nThis update ships updated CPU microcode for some types of Intel CPUs and\nprovides mitigations for the Special Register Buffer Data Sampling\n(CVE-2020-0543), Vector Register Sampling (CVE-2020-0548) and L1D\nEviction Sampling (CVE-2020-0549) hardware vulnerabilities.\n\nThe microcode update for HEDT and Xeon CPUs with signature 0x50654 which\nwas reverted in DSA 4565-2 is now included again with a fixed release.\n\nThe upstream update for Skylake-U/Y (signature 0x406e3) had to be\nexcluded from this update due to reported hangs on boot.\n\nFor details refer to\nhttps://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html\nhttps://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html\n\nFor the oldstable distribution (stretch), these problems have been fixed\nin version 3.20200609.2~deb9u1.\n\nFor the stable distribution (buster), these problems have been fixed in\nversion 3.20200609.2~deb10u1.\n\nWe recommend that you upgrade your intel-microcode packages.\n\nFor the detailed security status of intel-microcode please refer to its\nsecurity tracker page at:\nhttps://security-tracker.debian.org/tracker/intel-microcode\n\nFurther information about Debian Security Advisories, how to apply\nthese updates to your system and frequently asked questions can be\nfound at: https://www.debian.org/security/\n\nMailing list: debian-security-announce@lists.debian.org\n", "edition": 1, "modified": "2020-06-11T15:22:01", "published": "2020-06-11T15:22:01", "id": "DEBIAN:DSA-4701-1:BB3B8", "href": "https://lists.debian.org/debian-security-announce/debian-security-announce-2020/msg00105.html", "title": "[SECURITY] [DSA 4701-1] intel-microcode security update", "type": "debian", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-14T00:52:44", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "Package : intel-microcode\nVersion : 3.20200609.2~deb8u1\nCVE ID : CVE-2020-0543 CVE-2020-0548 CVE-2020-0549\n\n\nThe following CVE(s) were reported against src:intel-microcode.\n\nCVE-2020-0543\n\n A new domain bypass transient execution attack known as Special\n Register Buffer Data Sampling (SRBDS) has been found. This flaw\n allows data values from special internal registers to be leaked\n by an attacker able to execute code on any core of the CPU. An\n unprivileged, local attacker can use this flaw to infer values\n returned by affected instructions known to be commonly used\n during cryptographic operations that rely on uniqueness, secrecy,\n or both.\n\nCVE-2020-0548\n\n A flaw was found in Intel processors where a local attacker is\n able to gain information about registers used for vector\n calculations by observing register states from other processes\n running on the system. This results in a race condition where\n store buffers, which were not cleared, could be read by another\n process or a CPU sibling. The highest threat from this\n vulnerability is data confidentiality where an attacker could\n read arbitrary data as it passes through the processor.\n\nCVE-2020-0549\n\n A microarchitectural timing flaw was found on some Intel\n processors. A corner case exists where data in-flight during the\n eviction process can end up in the \u201cfill buffers\u201d and not properly\n cleared by the MDS mitigations. The fill buffer contents (which\n were expected to be blank) can be inferred using MDS or TAA style\n attack methods to allow a local attacker to infer fill buffer\n values.\n\nFor Debian 8 "Jessie", these problems have been fixed in version\n3.20200609.2~deb8u1.\n\nWe recommend that you upgrade your intel-microcode packages.\n\nFurther information about Debian LTS security advisories, how to apply\nthese updates to your system and frequently asked questions can be\nfound at: https://wiki.debian.org/LTS\n\n\nBest,\nUtkarsh\n", "edition": 1, "modified": "2020-06-13T15:30:07", "published": "2020-06-13T15:30:07", "id": "DEBIAN:DLA-2248-1:806E4", "href": "https://lists.debian.org/debian-lts-announce/2020/debian-lts-announce-202006/msg00019.html", "title": "[SECURITY] [DLA 2248-1] intel-microcode security update", "type": "debian", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "suse": [{"lastseen": "2020-06-11T01:22:19", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "This update for ucode-intel fixes the following issues:\n\n Updated Intel CPU Microcode to 20200602 (prerelease) (bsc#1172466)\n\n This update contains security mitigations for:\n\n - CVE-2020-0543: Fixed a side channel attack against special registers\n which could have resulted in leaking of read values to cores other than\n the one which called it. This attack is known as Special Register\n Buffer Data Sampling (SRBDS) or "CrossTalk" (bsc#1154824).\n - CVE-2020-0548,CVE-2020-0549: Additional ucode updates were supplied to\n mitigate the Vector Register and L1D Eviction Sampling aka\n "CacheOutAttack" attacks. (bsc#1156353)\n\n Microcode Table:\n\n Processor Identifier Version Products Model\n Stepping F-MO-S/PI Old->New\n ---- new platforms ----------------------------------------\n ---- updated platforms ------------------------------------ HSW\n C0 6-3c-3/32 00000027->00000028 Core Gen4 BDW-U/Y E0/F0\n 6-3d-4/c0 0000002e->0000002f Core Gen5 HSW-U C0/D0 6-45-1/72\n 00000025->00000026 Core Gen4 HSW-H C0 6-46-1/32\n 0000001b->0000001c Core Gen4 BDW-H/E3 E0/G0 6-47-1/22\n 00000021->00000022 Core Gen5 SKL-U/Y D0 6-4e-3/c0\n 000000d6->000000dc Core Gen6 Mobile SKL-U23e K1 6-4e-3/c0\n 000000d6->000000dc Core Gen6 Mobile SKX-SP B1 6-55-3/97\n 01000151->01000157 Xeon Scalable SKX-SP H0/M0/U0 6-55-4/b7\n 02000065->02006906 Xeon Scalable SKX-D M1 6-55-4/b7\n 02000065->02006906 Xeon D-21xx CLX-SP B0 6-55-6/bf\n 0400002c->04002f01 Xeon Scalable Gen2 CLX-SP B1 6-55-7/bf\n 0500002c->04002f01 Xeon Scalable Gen2 SKL-H/S R0/N0 6-5e-3/36\n 000000d6->000000dc Core Gen6; Xeon E3 v5 AML-Y22 H0\n 6-8e-9/10 000000ca->000000d6 Core Gen8 Mobile KBL-U/Y H0\n 6-8e-9/c0 000000ca->000000d6 Core Gen7 Mobile CFL-U43e D0\n 6-8e-a/c0 000000ca->000000d6 Core Gen8 Mobile WHL-U W0\n 6-8e-b/d0 000000ca->000000d6 Core Gen8 Mobile AML-Y42 V0\n 6-8e-c/94 000000ca->000000d6 Core Gen10 Mobile CML-Y42 V0\n 6-8e-c/94 000000ca->000000d6 Core Gen10 Mobile WHL-U V0\n 6-8e-c/94 000000ca->000000d6 Core Gen8 Mobile KBL-G/H/S/E3 B0\n 6-9e-9/2a 000000ca->000000d6 Core Gen7; Xeon E3 v6 CFL-H/S/E3\n U0 6-9e-a/22 000000ca->000000d6 Core Gen8 Desktop, Mobile, Xeon E\n CFL-S B0 6-9e-b/02 000000ca->000000d6 Core Gen8\n CFL-H/S P0 6-9e-c/22 000000ca->000000d6 Core Gen9\n CFL-H R0 6-9e-d/22 000000ca->000000d6 Core Gen9 Mobile\n\n Also contains the Intel CPU Microcode update to 20200520:\n\n Processor Identifier Version Products Model\n Stepping F-MO-S/PI Old->New\n ---- new platforms ----------------------------------------\n ---- updated platforms ------------------------------------ SNB-E/EN/EP\n C1/M0 6-2d-6/6d 0000061f->00000621 Xeon E3/E5, Core X SNB-E/EN/EP\n C2/M1 6-2d-7/6d 00000718->0000071a Xeon E3/E5, Core X\n\n This update was imported from the SUSE:SLE-15-SP1:Update update project.\n\n", "edition": 1, "modified": "2020-06-11T00:12:43", "published": "2020-06-11T00:12:43", "id": "OPENSUSE-SU-2020:0791-1", "href": "http://lists.opensuse.org/opensuse-security-announce/2020-06/msg00016.html", "title": "Security update for ucode-intel (moderate)", "type": "suse", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "centos": [{"lastseen": "2020-06-10T21:29:51", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "**CentOS Errata and Security Advisory** CESA-2020:2432\n\n\nSecurity Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.\n\nBug Fix(es):\n\n* Update Intel CPU microcode to microcode-20200602 release, addresses:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n- Change the URL in the intel-microcode2ucode.8 to point to the GitHub\n repository since the microcode download section at Intel Download Center\n does not exist anymore.\n\n* Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models.\n\n* Re-generate initramfs not only for the currently running kernel,\n but for several recently installed kernels as well.\n\n* Avoid find being SIGPIPE'd on early \"grep -q\" exit in the dracut script.\n\n* Update stale posttrans dependency, add triggers for proper handling\n of the debug kernel flavour along with kernel-rt.\n\n**Merged security bulletin from advisories:**\nhttp://lists.centos.org/pipermail/centos-announce/2020-June/035754.html\n\n**Affected packages:**\nmicrocode_ctl\n\n**Upstream details at:**\n", "edition": 1, "modified": "2020-06-10T17:22:53", "published": "2020-06-10T17:22:53", "id": "CESA-2020:2432", "href": "http://lists.centos.org/pipermail/centos-announce/2020-June/035754.html", "title": "microcode_ctl security update", "type": "centos", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-10T21:24:44", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0549", "CVE-2020-0543", "CVE-2020-0548"], "description": "**CentOS Errata and Security Advisory** CESA-2020:2433\n\n\nThe microcode_ctl packages provide microcode updates for Intel and AMD processors.\n\nSecurity Fix(es):\n\n* hw: Special Register Buffer Data Sampling (SRBDS) (CVE-2020-0543)\n\n* hw: L1D Cache Eviction Sampling (CVE-2020-0549)\n\n* hw: Vector Register Data Sampling (CVE-2020-0548)\n\nFor more details about the security issue(s), including the impact, a CVSS score, acknowledgments, and other related information, refer to the CVE page(s) listed in the References section.\n\nBug Fix(es) and Enhancement(s):\n\n* Update Intel CPU microcode to microcode-20200602 release, addresses:\n - Update of 06-3c-03/0x32 (HSW C0) microcode from revision 0x27 up to 0x28;\n - Update of 06-3d-04/0xc0 (BDW-U/Y E0/F0) microcode from revision 0x2e\n up to 0x2f;\n - Update of 06-45-01/0x72 (HSW-U C0/D0) microcode from revision 0x25\n up to 0x26;\n - Update of 06-46-01/0x32 (HSW-H C0) microcode from revision 0x1b up to 0x1c;\n - Update of 06-47-01/0x22 (BDW-H/Xeon E3 E0/G0) microcode from revision 0x21\n up to 0x22;\n - Update of 06-4e-03/0xc0 (SKL-U/Y D0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-55-03/0x97 (SKX-SP B1) microcode from revision 0x1000151\n up to 0x1000157;\n - Update of 06-55-04/0xb7 (SKX-SP H0/M0/U0, SKX-D M1) microcode\n (in intel-06-55-04/intel-ucode/06-55-04) from revision 0x2000065\n up to 0x2006906;\n - Update of 06-55-06/0xbf (CLX-SP B0) microcode from revision 0x400002c\n up to 0x4002f01;\n - Update of 06-55-07/0xbf (CLX-SP B1) microcode from revision 0x500002c\n up to 0x5002f01;\n - Update of 06-5e-03/0x36 (SKL-H/S R0/N0) microcode from revision 0xd6\n up to 0xdc;\n - Update of 06-8e-09/0x10 (AML-Y22 H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-09/0xc0 (KBL-U/Y H0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0a/0xc0 (CFL-U43e D0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0b/0xd0 (WHL-U W0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-8e-0c/0x94 (AML-Y42 V0, CML-Y42 V0, WHL-U V0) microcode\n from revision 0xca up to 0xd6;\n - Update of 06-9e-09/0x2a (KBL-G/H/S/X/Xeon E3 B0) microcode from revision\n 0xca up to 0xd6;\n - Update of 06-9e-0a/0x22 (CFL-H/S/Xeon E3 U0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0b/0x02 (CFL-S B0) microcode from revision 0xca up to 0xd6;\n - Update of 06-9e-0c/0x22 (CFL-H/S P0) microcode from revision 0xca\n up to 0xd6;\n - Update of 06-9e-0d/0x22 (CFL-H R0) microcode from revision 0xca up to 0xd6.\n\n* Update Intel CPU microcode to microcode-20200520 release:\n - Update of 06-2d-06/0x6d (SNB-E/EN/EP C1/M0) microcode from revision 0x61f\n up to 0x621;\n - Update of 06-2d-07/0x6d (SNB-E/EN/EP C2/M1) microcode from revision 0x718\n up to 0x71a;\n - Update of 06-7e-05/0x80 (ICL-U/Y D1) microcode from revision 0x46\n up to 0x78.\n\n(BZ#1839193)\n\n* Narrow down SKL-SP/W/X blacklist to exclude Server/FPGA/Fabric segment\n models. (BZ#1835555)\n\n**Merged security bulletin from advisories:**\nhttp://lists.centos.org/pipermail/centos-announce/2020-June/035752.html\n\n**Affected packages:**\nmicrocode_ctl\n\n**Upstream details at:**\n", "edition": 1, "modified": "2020-06-10T17:17:14", "published": "2020-06-10T17:17:14", "id": "CESA-2020:2433", "href": "http://lists.centos.org/pipermail/centos-announce/2020-June/035752.html", "title": "microcode_ctl security update", "type": "centos", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "archlinux": [{"lastseen": "2020-09-22T18:36:39", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543", "CVE-2020-0548", "CVE-2020-0549"], "description": "Arch Linux Security Advisory ASA-202006-10\n==========================================\n\nSeverity: High\nDate : 2020-06-13\nCVE-ID : CVE-2020-0543 CVE-2020-0548 CVE-2020-0549\nPackage : intel-ucode\nType : information disclosure\nRemote : No\nLink : https://security.archlinux.org/AVG-1187\n\nSummary\n=======\n\nThe package intel-ucode before version 20200609-1 is vulnerable to\ninformation disclosure.\n\nResolution\n==========\n\nUpgrade to 20200609-1.\n\n# pacman -Syu \"intel-ucode>=20200609-1\"\n\nThe problems have been fixed upstream in version 20200609.\n\nWorkaround\n==========\n\nNone.\n\nDescription\n===========\n\n- CVE-2020-0543 (information disclosure)\n\nA new domain bypass transient execution attack known as Special\nRegister Buffer Data Sampling (SRBDS) has been found. This flaw allows\ndata values from special internal registers to be leaked by an attacker\nable to execute code on any core of the CPU. An unprivileged, local\nattacker can use this flaw to infer values returned by affected\ninstructions known to be commonly used during cryptographic operations\nthat rely on uniqueness, secrecy, or both.\n\n- CVE-2020-0548 (information disclosure)\n\nA flaw was found in Intel processors where a local attacker is able to\ngain information about registers used for vector calculations by\nobserving register states from other processes running on the system.\nThis results in a race condition where store buffers, which were not\ncleared, could be read by another process or a CPU sibling. The highest\nthreat from this vulnerability is data confidentiality where an\nattacker could read arbitrary data as it passes through the processor.\n\n- CVE-2020-0549 (information disclosure)\n\nA microarchitectural timing flaw was found on some Intel processors. A\ncorner case exists where data in-flight during the eviction process can\nend up in the \u201cfill buffers\u201d and not properly cleared by the MDS\nmitigations. The fill buffer contents (which were expected to be blank)\ncan be inferred using MDS or TAA style attack methods to allow a local\nattacker to infer fill buffer values.\n\nImpact\n======\n\nA local unprivileged attacker with access to an affected CPU can read\nprotected memory through a shared buffer on an SGX enclave or CPU core.\n\nReferences\n==========\n\nhttps://software.intel.com/security-software-guidance/insights/deep-dive-special-register-buffer-data-sampling\nhttps://blogs.intel.com/technology/2020/06/ipas-security-advisories-for-june-2020/#gs.6uyhri\nhttps://cacheoutattack.com/CacheOut.pdf\nhttps://software.intel.com/security-software-guidance/software-guidance/l1d-eviction-sampling\nhttps://blogs.intel.com/technology/2020/01/ipas-intel-sa-00329/\nhttps://access.redhat.com/solutions/l1d-cache-eviction-and-vector-register-sampling\nhttps://security.archlinux.org/CVE-2020-0543\nhttps://security.archlinux.org/CVE-2020-0548\nhttps://security.archlinux.org/CVE-2020-0549", "modified": "2020-06-13T00:00:00", "published": "2020-06-13T00:00:00", "id": "ASA-202006-10", "href": "https://security.archlinux.org/ASA-202006-10", "type": "archlinux", "title": "[ASA-202006-10] intel-ucode: information disclosure", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "hp": [{"lastseen": "2020-12-24T13:21:25", "bulletinFamily": "software", "cvelist": ["CVE-2020-0549", "CVE-2020-0548"], "description": "## Potential Security Impact\nInformation Disclosure \n\n**Source:** HP, HP Product Security Response Team (PSRT) \n\n**Reported By:** Intel \n\n## VULNERABILITY SUMMARY\nIntel has informed HP of a potential security vulnerability involving cleanup errors in some data cache evictions in some Intel\u00ae Processors that may allow an authenticated user to potentially enable information disclosure via local access.\n\n## RESOLUTION\nIntel has released microcode updates to mitigate the potential vulnerability. HP has identified the affected platforms and the corresponding SoftPaq updated versions. See the affected platforms listed below.\n", "edition": 4, "modified": "2020-10-26T00:00:00", "published": "2020-06-09T00:00:00", "id": "HP:C06657032", "href": "https://support.hp.com/us-en/document/c06657032", "title": "HPSBHF03670 rev. 2 - Intel\u00ae Processors Data Leakage Advisory", "type": "hp", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "threatpost": [{"lastseen": "2020-04-09T11:26:50", "bulletinFamily": "info", "cvelist": ["CVE-2020-0548", "CVE-2020-0549"], "description": "Researchers have identified a new speculative execution type attack, dubbed CacheOut, that could allow attackers to trigger data leaks from most Intel CPUs. The more serious of the two bugs, revealed Monday, is rated medium severity by Intel, who said fixes for both flaws are on the way.\n\nThe more serious of the two CacheOut bugs, tracked as CVE-2020-0549, is a CPU vulnerability that allows an attacker to target data stored within the OS kernel, co-resident virtual machines and even within Intel\u2019s Software Guard Extensions (SGX) enclave, a trusted execution environment on Intel processors.\n\n\u201cIn this work we present CacheOut, a new microarchitectural attack that is capable of bypassing Intel\u2019s buffer overwrite countermeasures,\u201d wrote researcher Stephan van Schaik of the University of Michigan and colleagues in [a research report](<https://cacheoutattack.com/>) made public Monday.\n\n[](<https://threatpost.com/newsletter-sign/>)\n\nThose \u201ccountermeasures\u201d refer to Intel\u2019s mitigation efforts for prior speculative execution attacks RIDL, Fallout, and ZombieLoad. CacheOut is similarly a Microarchitectural Data Sampling (MDS) or Zombieload flaw. It comes on the heels of two separate MDS patches released this past May and November.\n\nThe CacheOut vulnerabilities impact users running [CPUs released before Q4 2019](<https://software.intel.com/security-software-guidance/insights/processors-affected-l1d-eviction-sampling>), according to researchers. Also impacted are cloud providers, hypervisors and associated virtual machines. Researchers said CPUs made by IBM and ARM may also be affected.\n\nIn a [security bulletin issued Monday](<https://blogs.intel.com/technology/2020/01/ipas-intel-sa-00329/#gs.ve0udi>), Intel clarified that the medium-severity vulnerability (CVE-2020-0549) \u201chas little to no impact in virtual environments that have applied L1 Terminal Fault mitigations.\u201d\n\nIntel said patches to mitigate against CacheOut are forthcoming and that it will address the issue in the near future.\n\n\u201cIntel recommends that users of affected Intel Processors check with their system manufacturers and system software vendors and update to the latest microcode update when available,\u201d according [to the company](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>).\n\nResearchers also said that the vulnerability can be used to exploit an unmodified Linux kernel. \u201cMore specifically, we demonstrate attacks for breaking kernel address space layout randomization (KASLR) and recovering secret kernel stack canaries,\u201d researcher wrote.\n\nIntel is calls the flaw a \u201cL1D Eviction Sampling issue\u201d. L1 refers to the cache and pools of memory that contain the leak-able data. Intel said it is not aware of any related attacks exploiting the flaws.\n\n\u201cCacheOut demonstrates that [previous] this mitigation [are] incomplete, as we can force the victim\u2019s data out of the L1-D Cache into the microarchitectural buffers after the operating system clears them. We then subsequently leak the contents of the buffers and obtain the victim\u2019s data,\u201d researchers wrote.\n\nThe second less severe flaw is being tracked as CVE-2020-0548, which has a CVSS rating of 2.8 or low. Intel describes the flaw as a Vector Register Sampling bug. \u201cCleanup errors in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access,\u201d according to the Intel advisory.\n", "modified": "2020-01-28T22:58:46", "published": "2020-01-28T22:58:46", "id": "THREATPOST:7FB07E6C8DF569F394D4B277BFE12285", "href": "https://threatpost.com/new-cacheout-attack-targets-intel-cpus/152323/", "type": "threatpost", "title": "New \u2018CacheOut\u2019 Attack Targets Intel CPUs", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "thn": [{"lastseen": "2020-06-10T14:24:08", "bulletinFamily": "info", "cvelist": ["CVE-2020-0543", "CVE-2020-0549"], "description": "[](<https://thehackernews.com/images/-q7AM3dKlVhs/XuCzPPAlgcI/AAAAAAAA25E/9QOeNB3KQKAI5ucaLEW84YPX5tZledYpACLcBGAsYHQ/s728-e100/intel-cpu-side-channel-attack.jpg>)\n\nCybersecurity researchers have discovered two distinct attacks that could be exploited against modern Intel processors to leak sensitive information from the CPU's trusted execution environments (TEE). \n \nCalled [SGAxe](<https://sgaxe.com/>), the first of the flaws is an evolution of the previously uncovered [CacheOut attack](<https://thehackernews.com/2020/01/new-cacheout-attack-leaks-data-from.html>) (CVE-2020-0549) earlier this year that allows an attacker to retrieve the contents from the CPU's L1 Cache. \n \n\"By using the extended attack against the Intel-provided and signed architectural SGX enclaves, we retrieve the secret attestation key used for cryptographically proving the genuinity of enclaves over the network, allowing us to pass fake enclaves as genuine,\" a group of academics from the University of Michigan said. \n \nThe second line of attack, dubbed [CrossTalk](<https://www.vusec.net/projects/crosstalk/>) by researchers from the VU University Amsterdam, enables attacker-controlled code executing on one CPU core to target SGX enclaves running on a completely different core, and determine the enclave's private keys. \n\n\n \nA TEE, like Intel's Software Guard Extensions ([SGX](<https://software.intel.com/content/www/us/en/develop/topics/software-guard-extensions.html>)), refers to a secure enclave, an area within a processor that ensures confidentiality and integrity of code and data. It offers safeguards against the modification of sensitive software and data by malicious actors that may have broken into the target (virtual) machine. \n \n\n\n## SGAxe Attack: Extracting Sensitive Data From SGX Enclaves\n\n \nSGAxe builds on the CacheOut speculative execution attack to steal SGX data. According to the researchers, while Intel took steps to address side-channel attacks against SGX via several microcode updates and new architectures, the mitigations have proven ineffective. \n \nThat exploit, as a result, results in a [transient execution attack](<https://en.wikipedia.org/wiki/Transient_execution_CPU_vulnerability>) that can recover SGX cryptographic keys from a fully updated Intel machine, which is trusted by Intel's attestation server. \n \n[Attestation](<https://software.intel.com/content/www/us/en/develop/topics/software-guard-extensions/attestation-services.html>) is a mechanism offered as part of SGX that lets enclaves prove to third parties that they have been correctly initialized on a genuine Intel processor. The idea is to ensure that the software running inside the CPU hasn't tampered with and to have increased confidence that the software is running inside the enclave. \n \n\"In a nutshell, we use CacheOut to recover the sealing keys from within the address space of Intel's production quoting enclave,\" the researchers stated. \"Finally, we use the recovered sealing keys in order to decrypt the long term storage of the quoting enclave, obtaining the machines EPID attestation keys.\" \n \n\n\n[](<https://thehackernews.com/images/-mhMUHEUbxTM/XuDY5CGSUAI/AAAAAAAA25Q/FZnYFSurLQIyU0NBZmx-oyn5FxMxb1BfQCLcBGAsYHQ/s728-e100/intel-cpu-side-channel-attack.jpg>)\n\n \nBy breaking this trust, SGAxe makes it easy for an attacker to create a rogue enclave that passes Intel's attestation mechanism, resulting in loss of security guarantees. \n \n\"With the machine's production attestation keys compromised, any secrets provided by [the] server are immediately readable by the client's untrusted host application, while all outputs allegedly produced by enclaves running on the client cannot be trusted for correctness,\" the researchers said. \"This effectively renders SGX-based DRM applications useless, as any provisioned secret can be trivially recovered.\" \n \nAlthough Intel issued fixes for CacheOut [back in January](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>) via a microcode update to OEM vendors and subsequently via BIOS updates to end-users, mitigations for SGAxe will require patching the root cause behind CacheOut (aka [L1D Eviction Sampling](<https://software.intel.com/security-software-guidance/software-guidance/l1d-eviction-sampling>)). \n\n\n \n\"It is important to note that SGAxe relies on CVE-2020-0549 which has been mitigated in microcode (confirmed by the researchers in their updated CacheOut paper) and distributed out to the ecosystem,\" Intel said in a [security advisory](<https://blogs.intel.com/technology/2020/06/ipas-security-advisories-for-june-2020/>). \n \nThe chipmaker will also perform a Trusted Compute Base (TCB) recovery to invalidate all previously signed attestation keys. \n \n\"This process will ensure that your system is in a secure state such that your system is able to use remote attestation again,\" the researchers stated. \n \n\n\n## CrossTalk Attack: Leaking Information Across CPU cores\n\n \nCrossTalk ([CVE-2020-0543](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html>)), the second SGX exploit, is what the VU University calls an [MDS](<https://mdsattacks.com/>) (Microarchitectural Data Sampling) attack. It takes advantage of a \"staging\" buffer that's readable across all CPU cores to mount transient execution attacks across the cores and extract the entire ECDSA private key of a secure enclave running on a separate CPU core. \n \n\"The staging buffer retains the results of previously executed offcore-instructions across all CPU cores,\" the researchers observed. \"For instance, it contains the random numbers returned by the offcore hardware DRNG, bootguard status hashes, and other sensitive data.\" \n \n\n\n[](<https://thehackernews.com/images/-iWjE54UP8Bo/XuCxSQbHsFI/AAAAAAAA244/5mREm6oPAV8awl7q3GesRBZb0kfbij_ygCLcBGAsYHQ/s728-e100/intel-cpu-side-channel-attack.jpg>)\n\n \nPut differently, CrossTalk works by reading the staging buffer during transient execution in order to leak sensitive data accessed by previously executed victim instructions. \n \nThe fact that the buffer retains output from [RDRAND and RDSEED](<https://software.intel.com/content/www/us/en/develop/blogs/the-difference-between-rdrand-and-rdseed.html>) instructions makes it possible for an unauthorized party to track the random numbers generated, and therefore compromise the cryptographic operations that underpin the SGX enclave, including the aforementioned [remote attestation process](<https://download.01.org/intel-sgx/dcap-1.0.1/docs/Intel_SGX_DCAP_ECDSA_Orientation.pdf>). \n \n\n\n \nWith Intel CPUs released from 2015 to 2019, counting Xeon E3 and E CPUs, susceptible to the attacks, VU University researchers said it shared with Intel a proof-of-concept demonstrating the leakage of staging buffer content in September 2018, followed by a PoC implementing cross-core RDRAND/RDSEED leakage in July 2019. \n \n\"Mitigations against existing transient execution attacks are largely ineffective,\" the team summarized. \"The majority of current mitigations rely on spatial isolation on boundaries which are no longer applicable due to the cross-core nature of these attacks. New microcode updates which lock the entire memory bus for these instructions can mitigate these attacks\u2014but only if there are no similar problems which have yet to be found.\" \n \nIn response to the findings, Intel addressed the flaw in a microcode update distributed to software vendors yesterday after a prolonged 21-month disclosure period due to the difficulty in implementing a fix. \n \nThe company has recommended users of affected processors update to the latest version of the firmware provided by system manufacturers to address the issue. \n\n\nFound this article interesting? Follow THN on [Facebook](<https://www.facebook.com/thehackernews>), [Twitter _\uf099_](<https://twitter.com/thehackersnews>) and [LinkedIn](<https://www.linkedin.com/company/thehackernews/>) to read more exclusive content we post.\n", "modified": "2020-06-10T12:59:04", "published": "2020-06-10T12:59:00", "id": "THN:8841D27BD6D8D04E9583E7E0F20898D5", "href": "https://thehackernews.com/2020/06/intel-sgaxe-crosstalk-attacks.html", "type": "thn", "title": "Intel CPUs Vulnerable to New 'SGAxe' and 'CrossTalk' Side-Channel Attacks", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-01-28T17:34:12", "bulletinFamily": "info", "cvelist": ["CVE-2020-0549"], "description": "[](<https://1.bp.blogspot.com/-zzjgSUL88QQ/XjBhSs8OEVI/AAAAAAAA2O4/o96M1JF3gB4j-jmcJF4B2UAgrUGJ-hZVwCLcBGAsYHQ/s728-e100/intel-processor-speculative-execution-vulnerability.jpg>)\n\nAnother month, another [speculative execution vulnerability](<https://thehackernews.com/2018/11/meltdown-spectre-vulnerabilities.html>) found in Intel processors. \n \nIf your computer is running any modern Intel CPU built before October 2018, it's likely vulnerable to a newly discovered hardware issue that could allow attackers to leak sensitive data from the OS kernel, co-resident virtual machines, and even from [Intel's secured SGX enclave](<https://thehackernews.com/2019/12/intel-sgx-voltage-attack.html>). \n \nDubbed **CacheOut** a.k.a. L1 Data Eviction Sampling (**L1DES**) and assigned **CVE-2020-0549**, the new microarchitectural attack allows an attacker to choose which data to leak from the CPU's L1 Cache, unlike previously demonstrated [MDS attacks](<https://thehackernews.com/2019/05/intel-processor-vulnerabilities.html>) where attackers need to wait for the targeted data to be available. \n \nAccording to a team of academic researchers, the newly-discovered speculative execution attacks can leak information across multiple security boundaries, including those between hyper-threads, virtual machines, and processes, and between user space and the operating system kernel, and from SGX enclaves. \n\n\n \n\"CacheOut can leak information from other processes running on the same thread, or across threads on the same CPU core,\" the researchers [said](<https://cacheoutattack.com/>). \"CacheOut violates the operating system's privacy by extracting information from it that facilitates other attacks, such as buffer overflow attacks.\" \n \nMore precisely, the attack enables a malicious program to force the victim's data out of the L1-D Cache into leaky buffers after the operating system clears them, and then subsequently leak the contents of the buffers and obtain the victim's data. \n \n\n\n[](<https://1.bp.blogspot.com/-4sVlxr8sLEo/XjBiJaFu3WI/AAAAAAAA2PA/lGNWkt143h40zJDfqfbl2iImjjMAYpuIwCLcBGAsYHQ/s728-e100/intel-processors.jpg>)\n\n \nResearchers at the universities of Adelaide and Michigan demonstrated: \n \n\n\n * the effectiveness of CacheOut in violating process isolation by recovering AES keys and plaintexts from an OpenSSL-based victim,\n * practical exploits for completely de-randomizing Linux's kernel ASLR, and for recovering secret stack canaries from the Linux kernel,\n * how CacheOut effectively violates the isolation between two virtual machines running on the same physical core,\n * how CacheOut could also be used to breach the confidentiality SGX guarantees by reading out the contents of a secure enclave,\n * how some of the latest Meltdown-resistant Intel CPUs are still vulnerable, despite all of the most recent patches and mitigations.\n \nBesides this, according to researchers, it's currently unlikely for Antivirus products to detect and block CacheOut attacks, and since the exploit does not leave any traces in the traditional log file, it's also \"very unlikely\" to identify whether someone has exploited the flaw or not. \n\n\n \nTo be noted, CacheOut flaw can't be exploited remotely from a web browser and also doesn't affect AMD processors. \n \nBased on researchers findings, Intel yesterday released [new microcode updates](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>) for [affected processors](<https://software.intel.com/security-software-guidance/insights/processors-affected-l1d-eviction-sampling>) that eventually turns off **Transactional Memory Extension** (TSX) on the CPUs. \n \n\"Software [update] can mitigate these issues at the cost of features and/or performance. We hope that somewhere in the future, Intel will release processors with in-silicon fixes against this issue,\" the researchers said. \n \nThough most cloud providers have rolled out patches to their infrastructures, other users can also mitigate the cross-thread leakage by disabling Intel hyper-threading for systems where security is more important. \n \nFurthermore, neither Intel nor the researchers have released exploit code, which indicates there's no direct and immediate threat. \n\n\nHave something to say about this article? Comment below or share it with us on [Facebook](<https://www.facebook.com/thehackernews>), [Twitter](<https://twitter.com/thehackersnews>) or our [LinkedIn Group](<https://www.linkedin.com/company/thehackernews/>).\n", "modified": "2020-01-28T16:36:17", "published": "2020-01-28T16:36:00", "id": "THN:2CDA9FC212AD7424B67DFBA5344BC5BD", "href": "https://thehackernews.com/2020/01/new-cacheout-attack-leaks-data-from.html", "type": "thn", "title": "New 'CacheOut' Attack Leaks Data from Intel CPUs, VMs and SGX Enclave", "cvss": {"score": 0.0, "vector": "NONE"}}], "lenovo": [{"lastseen": "2020-10-14T09:02:18", "bulletinFamily": "info", "cvelist": ["CVE-2020-0549", "CVE-2020-0550", "CVE-2020-0548"], "description": "****\n\n**Lenovo Security Advisory:** LEN-30044\n\n**Potential Impact**: Information Disclosure\n\n**Severity:** Medium\n\n**Scope of Impact:** Industry-wide\n\n**CVE Identifier:** CVE-2020-0548, CVE-2020-0549, CVE-2020-0550\n\n**Summary Description: **\n\nIntel reported potential security vulnerabilities in some Intel Processors that may allow information disclosure. These vulnerabilities may be referred to as Vector Register Sampling (CVE-2020-0548) and L1D Eviction Sampling or CacheOut (CVE-2020-0549). Refer to [Intel\u2019s Security Advisory](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>) for additional information.\n\nCVE-2020-0548: Cleanup errors in some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\nCVE-2020-0549: Cleanup errors in some data cache evictions for some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\nCVE-2020-0550: Improper data forwarding in some data cache for some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\n**Mitigation Strategy for Customers (what you should do to protect yourself): **\n\nIntel expects to release microcode updates for affected processors. Lenovo will publish fixes for affected systems once microcode updates are available from Intel. Until mitigations are available, the following guidance can be followed to reduce the likelihood of a successful attack from these vulnerabilities.\n\nCVE-2020-0548: Intel recommends applying previous MDS mitigations described in [LEN-26696](<https://support.lenovo.com/us/en/product_security/LEN-26696>) to reduce the impact of this vulnerability.\n\nCVE-2020-0549: Intel recommends applying previous L1 Terminal Fault mitigations described in [LEN-24163](<https://support.lenovo.com/us/en/solutions/LEN-24163>) to reduce the impact of this vulnerability in virtual environments.\n\nCVE-2020-0550: Intel recommends applying previous L1 Terminal Fault mitigations described in [LEN-24163](<https://support.lenovo.com/us/en/solutions/LEN-24163>) to reduce the impact of this vulnerability in virtual environments.\n", "edition": 92, "modified": "2020-09-24T14:37:41", "published": "2020-01-28T17:40:36", "id": "LENOVO:PS500303-NOSID", "href": "https://support.lenovo.com/us/en/solutions/ps500303", "title": "Intel Processors Side Channel Data Leakage Vulnerabilities - Lenovo Support US", "type": "lenovo", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2021-02-21T03:28:05", "bulletinFamily": "info", "cvelist": ["CVE-2020-0549", "CVE-2020-0550", "CVE-2020-0548"], "description": "****\n\n**Lenovo Security Advisory:** LEN-30044\n\n**Potential Impact**: Information Disclosure\n\n**Severity:** Medium\n\n**Scope of Impact:** Industry-wide\n\n**CVE Identifier:** CVE-2020-0548, CVE-2020-0549, CVE-2020-0550\n\n**Summary Description: **\n\nIntel reported potential security vulnerabilities in some Intel Processors that may allow information disclosure. These vulnerabilities may be referred to as Vector Register Sampling (CVE-2020-0548) and L1D Eviction Sampling or CacheOut (CVE-2020-0549). Refer to [Intel\u2019s Security Advisory](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>) for additional information.\n\nCVE-2020-0548: Cleanup errors in some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\nCVE-2020-0549: Cleanup errors in some data cache evictions for some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\nCVE-2020-0550: Improper data forwarding in some data cache for some Intel Processors may allow an authenticated user to potentially enable information disclosure via local access.\n\n**Mitigation Strategy for Customers (what you should do to protect yourself): **\n\nIntel expects to release microcode updates for affected processors. Lenovo will publish fixes for affected systems once microcode updates are available from Intel. Until mitigations are available, the following guidance can be followed to reduce the likelihood of a successful attack from these vulnerabilities.\n\nCVE-2020-0548: Intel recommends applying previous MDS mitigations described in [LEN-26696](<https://support.lenovo.com/us/en/product_security/LEN-26696>) to reduce the impact of this vulnerability.\n\nCVE-2020-0549: Intel recommends applying previous L1 Terminal Fault mitigations described in [LEN-24163](<https://support.lenovo.com/us/en/solutions/LEN-24163>) to reduce the impact of this vulnerability in virtual environments.\n\nCVE-2020-0550: Intel recommends applying previous L1 Terminal Fault mitigations described in [LEN-24163](<https://support.lenovo.com/us/en/solutions/LEN-24163>) to reduce the impact of this vulnerability in virtual environments.\n", "edition": 31, "modified": "2020-10-21T21:17:26", "published": "2020-01-28T17:40:36", "id": "LENOVO:PS500303-INTEL-PROCESSORS-SIDE-CHANNEL-DATA-LEAKAGE-VULNERABILITIES-NOSID", "href": "https://support.lenovo.com/us/en/solutions/ps500303-intel-processors-side-channel-data-leakage-vulnerabilities", "title": "Intel Processors Side Channel Data Leakage Vulnerabilities - Lenovo Support US", "type": "lenovo", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-10-14T15:02:01", "bulletinFamily": "info", "cvelist": ["CVE-2020-0543"], "description": "**Lenovo Security Advisory:** LEN-30043\n\n**Potential Impact**: Information disclosure\n\n**Severity:** Medium\n\n**Scope of Impact:** Industry-wide\n\n**CVE Identifier:** CVE-2020-0543\n\n**Summary Description: **\n\nIntel reported potential security vulnerabilities in some Intel Processors that may allow information disclosure. This vulnerability may be referred to as Special Register Buffer Data Sampling (SRBDS) or CrossTalk. Refer to [Intel\u2019s Security Advisory](<https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00329.html>) for additional information.\n\n**Mitigation Strategy for Customers (what you should do to protect yourself): **\n\nIntel recommends updating system firmware to the version (or newer) indicated for your model in the Product Impact section below.\n", "edition": 50, "modified": "2020-09-24T14:37:06", "published": "2020-06-04T16:44:25", "id": "LENOVO:PS500327-NOSID", "href": "https://support.lenovo.com/us/en/product_security/ps500327", "title": "Intel Special Register Buffer Data Sampling Advisory - Lenovo Support US", "type": "lenovo", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "freebsd": [{"lastseen": "2020-12-28T17:20:57", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "\nIntel reports:\n\nIntel CPUs suffer Special Register Buffer Data Sampling vulnerability\n\n", "edition": 1, "modified": "2020-06-09T00:00:00", "published": "2020-06-09T00:00:00", "id": "FBCBA194-AC7D-11EA-8B5E-B42E99A1B9C3", "href": "https://vuxml.freebsd.org/freebsd/fbcba194-ac7d-11ea-8b5e-b42e99a1b9c3.html", "title": "Intel CPU issues", "type": "freebsd", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "citrix": [{"lastseen": "2020-12-24T11:42:43", "bulletinFamily": "software", "cvelist": ["CVE-2020-0543"], "description": "<section class=\"article-content\" data-swapid=\"ArticleContent\">\n<div class=\"content-block\" data-swapid=\"ContentBlock\"><div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"DescriptionofProblem\"> Description of Problem</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<p>Modern CPUs contain random number generators that provide entropy (randomness) to the software running on those processors to use for purposes such as generating cryptographic encryption keys. Software can obtain entropy by using the RDRAND and RDSEED instructions.</p>\n<p>A security issue has been identified in certain CPU hardware that may allow unprivileged code running on a host to observe the entropy provided by the CPU to other processes, virtual machines or the hypervisor that are, or have recently been, running, irrespective of whether they are running on the same processor core or thread. For example, if a process in one guest VM were to use the RDSEED instruction to get a random value to use as a secret encryption key, another process in a different VM might be able to observe the result of that RDSEED instruction and so determine the secret encryption key.</p>\n<p>This issue has the following identifier:</p>\n<ul>\n<li>CVE-2020-0543: Special Register Buffer Data Sampling Advisory</li>\n</ul>\n<p>Note that this issue only affects the confidentiality of the entropy returned by the CPU, not how random the value itself is.</p>\n<p>Note also that an attacker can only observe the entropy most recently returned by an RDSEED or RDRAND instruction on the system. If a further RDSEED or RDRAND instruction is executed on the system, the older result is no longer observable by an attacker.</p>\n<p>Although this is not a vulnerability in the Citrix Hypervisor (formerly Citrix XenServer) product, Citrix is providing hotfixes to mitigate this CPU issue. Hotfixes are available for all currently supported versions of Citrix Hypervisor up to and including Citrix Hypervisor 8.1. These hotfixes include updated CPU microcode which may have a noticeable performance impact on workloads that make significant use of RDRAND or RDSEED instructions.</p>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"MitigatingFactors\"> Mitigating Factors</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<p>Only certain Intel CPUs are affected by this issue; customers are recommended to contact their hardware vendor to determine if their system is affected.</p>\n<p>Customers with only AMD CPUs are not affected by this issue.</p>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"WhatCustomersShouldDo\"> What Customers Should Do</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<p>Hotfixes have been released to address these issues. Citrix recommends that affected customers install these hotfixes as soon as their patching schedule permits. The hotfixes can be downloaded from the following locations:</p>\n<p>Citrix Hypervisor 8.1: CTX272278 \u2013 <a href=\"https://support.citrix.com/article/CTX272278\">https://support.citrix.com/article/CTX272278</a></p>\n<p>Citrix Hypervisor 8.0: CTX272277 \u2013 <a href=\"https://support.citrix.com/article/CTX272277\">https://support.citrix.com/article/CTX272277</a></p>\n<p>Citrix XenServer 7.1 LTSR CU2: CTX272276 \u2013 <a href=\"https://support.citrix.com/article/CTX272276\">https://support.citrix.com/article/CTX272276</a></p>\n<p>Citrix XenServer 7.0: CTX272275 \u2013 <a href=\"https://support.citrix.com/article/CTX272275\">https://support.citrix.com/article/CTX272275</a><br/> </p>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"WhatCitrixIsDoing\"> What Citrix Is Doing</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<div>\n<div>\n<p>Citrix is notifying customers and channel partners about this potential security issue. This article is also available from the Citrix Knowledge Center at <u> <a href=\"http://support.citrix.com/\">http://support.citrix.com/</a></u>.</p>\n</div>\n</div>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"ObtainingSupportonThisIssue\"> Obtaining Support on This Issue</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<div>\n<div>\n<p>If you require technical assistance with this issue, please contact Citrix Technical Support. Contact details for Citrix Technical Support are available at <u> <a href=\"https://www.citrix.com/support/open-a-support-case.html\">https://www.citrix.com/support/open-a-support-case.html</a></u>. </p>\n</div>\n</div>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"ReportingSecurityVulnerabilities\"> Reporting Security Vulnerabilities</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<div>\n<div>\n<p>Citrix welcomes input regarding the security of its products and considers any and all potential vulnerabilities seriously. For guidance on how to report security-related issues to Citrix, please see the following document: CTX081743 \u2013 <a href=\"http://support.citrix.com/article/CTX081743\">Reporting Security Issues to Citrix</a></p>\n</div>\n</div>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n<div>\n<!--googleoff: all-->\n<h2 id=\"Changelog\"> Changelog</h2>\n<!--googleon: all-->\n<div>\n<div>\n<div>\n<table border=\"1\" cellpadding=\"1\" cellspacing=\"0\" width=\"100%\">\n<tbody>\n<tr>\n<td>Date </td>\n<td>Change</td>\n</tr>\n<tr>\n<td>2020-06-09</td>\n<td>Initial Publication</td>\n</tr>\n</tbody>\n</table>\n</div>\n</div>\n</div>\n<!--googleoff: all-->\n<hr/>\n</div>\n</div></div>\n</section>", "modified": "2020-06-09T04:00:00", "published": "2020-06-09T04:00:00", "id": "CTX275165", "href": "https://support.citrix.com/article/CTX275165", "type": "citrix", "title": "Citrix Hypervisor Security Updates", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "xen": [{"lastseen": "2020-06-09T21:22:05", "bulletinFamily": "software", "cvelist": ["CVE-2020-0543"], "description": "#### ISSUE DESCRIPTION\nThis issue is related to the MDS and TAA vulnerabilities. Please see <a href=\"https://xenbits.xen.org/xsa/advisory-297.html\">https://xenbits.xen.org/xsa/advisory-297.html</a> (MDS) and <a href=\"https://xenbits.xen.org/xsa/advisory-305.html\">https://xenbits.xen.org/xsa/advisory-305.html</a> (TAA) for details.\nCertain processor operations microarchitecturally need to read data from outside the physical core (e.g. to communicate with the random number generator). In some implementations, this operation is called a Special Register Read.\nIn some implementations, data are staged in a single shared buffer, and a full cache line at a time is returned to the core which made the Special Register Read. On parts vulnerable to MFBDS or TAA, an attacker may be able to access stale data requested by other cores in the system.\nFor more details, see: <a href=\"https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html\">https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00320.html</a>\n#### IMPACT\nAn attacker, which could include a malicious untrusted user process on a trusted guest, or an untrusted guest, can sample the contents of certain off-core accesses by other cores in the system.\nThis can include data whose use may depend on the secrecy of the value, such as data from the Random Number Generator (e.g. RDRAND/RDSEED instructions).\n#### VULNERABLE SYSTEMS\nSystems running all versions of Xen are affected.\nOnly x86 processors are vulnerable. ARM processors are not believed to be vulnerable.\nOnly Intel based processors are affected. Processors from other manufacturers (e.g. AMD) are not believed to be vulnerable.\nPlease consult the Intel Security Advisory for details on the affected processors.\n", "edition": 1, "modified": "2020-06-09T16:33:00", "published": "2020-06-09T16:33:00", "id": "XSA-320", "href": "http://xenbits.xen.org/xsa/advisory-320.html", "title": "Special Register Buffer speculative side channel", "type": "xen", "cvss": {"score": 0.0, "vector": "NONE"}}], "ics": [{"lastseen": "2021-02-24T09:27:17", "bulletinFamily": "info", "cvelist": ["CVE-2020-0543"], "description": "## 1\\. EXECUTIVE SUMMARY\n\n * **CVSS v3 5.5**\n * **ATTENTION:** Low skill level to exploit\n * **Vendor:** Siemens\n * **Equipment: **Siemens Industrial Products containing certain processors\n * **Vulnerability: **Exposure of Sensitive Information to an Unauthorized Actor\n\n## 2\\. UPDATE INFORMATION\n\nThis updated advisory is a follow-up to the advisory update titled ICSA-20-252-07 Siemens Industrial Products (Update B) that was published December 8, 2020, to the ICS webpage on us-cert.cisa.gov.\n\n## 3\\. RISK EVALUATION\n\nSuccessful exploitation of this vulnerability may allow an authenticated user to enable information disclosure via local access.\n\n## 4\\. TECHNICAL DETAILS\n\n### 4.1 AFFECTED PRODUCTS\n\n * SIMATIC Field PG M4: All versions.\n\n**\\--------- Begin Update C Part 1 of 2 ---------**\n\n * SIMATIC Field PG M5: All BIOS versions prior to v22.01.08\n * SIMATIC Field PG M6: All BIOS versions prior to v26.01.07\n\n**\\--------- End Update C Part 1 of 2 ---------**\n\n * SIMATIC Field PG M5: All versions\n * SIMATIC Field PG M6: All versions\n * SIMATIC IPC3000 SMART: All versions\n * SIMATIC IPC347E: All versions\n * SIMATIC IPC427D (incl. SIPLUS variants): All versions\n * SIMATIC IPC427E (incl. SIPLUS variants): All versions\n * SIMATIC IPC477D: All versions\n * SIMATIC IPC427E (incl. SIPLUS variants): All BIOS versions prior to 21.01.14\n * SIMATIC IPC477E: All BIOS versions prior to 21.01.14\n * SIMATIC IPC477E Pro: All BIOS versions prior to 21.01.14\n * SIMATIC IPC527G: All versions\n * SIMATIC IPC547E: All versions\n * SIMATIC IPC547G: All versions\n * SIMATIC IPC627D: All versions\n * SIMATIC IPC627E: All versions\n * SIMATIC IPC647D: All versions\n * SIMATIC IPC647E: All versions\n * SIMATIC IPC677D: All versions\n * SIMATIC IPC677E: All versions\n * SIMATIC IPC827D: All versions\n * SIMATIC IPC847D: All versions\n * SIMATIC IPC847E: All versions\n * SIMATIC ITP1000: All versions\n * SIMOTION P320-4E: All versions\n * SIMOTION P320-4S: All versions\n * SIMATIC IPC627E: All BIOS versions prior to v25.02.06\n * SIMATIC IPC647E: All BIOS versions prior to v25.02.06\n * SIMATIC IPC677E: All BIOS versions prior to v25.02.06\n * SIMATIC IPC847E: All BIOS versions prior to v25.02.06\n * SINUMERIK 828D (PPU.4 / PPU1740): All versions (Versions removed from the scope of this advisory)\n * SINUMERIK 840D sl (NCU730.3B): All versions (Versions removed from the scope of this advisory)\n * SINUMERIK ONE (NCU1750 / NCU1760): All versions (Versions removed from the scope of this advisory)\n\n### 4.2 VULNERABILITY OVERVIEW\n\n#### 4.2.1 [EXPOSURE OF SENSITIVE INFORMATION TO AN UNAUTHORIZED ACTOR CWE-200](<https://cwe.mitre.org/data/definitions/200.html>)\n\nIncomplete cleanup from specific special register read operations in some Intel processors may allow an authenticated user to potentially enable information disclosure via local access.\n\n[CVE-2020-0543](<http://web.nvd.nist.gov/view/vuln/detail?vulnId=CVE-2020-0543>) has been assigned to this vulnerability. A CVSS v3 base score of 5.5 has been calculated; the CVSS vector string is ([AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N](<https://www.first.org/cvss/calculator/3.0#CVSS:3.0/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:N/A:N/E:P/RL:O/RC:C>)).\n\n### 4.3 BACKGROUND\n\n * **CRITICAL INFRASTRUCTURE SECTORS:** Critical manufacturing\n * **COUNTRIES/AREAS DEPLOYED: **Worldwide\n * **COMPANY HEADQUARTERS LOCATION:** Germany\n\n### 4.4 RESEARCHER\n\nAlyssa Milburn, Hany Ragab, Kaveh Razavi, Herbert Bos, and Cristiano Giuffrida from the VUSec group at VU Amsterdam reported this vulnerability to Intel.\n\n## 5\\. MITIGATIONS\n\nSiemens recommends updating the following products to the most current BIOS version where available:\n\n * SIMATIC IPC627E IPC647E, IPC677E, and IPC847E BIOS to [v25.02.06](<https://support.industry.siemens.com/cs/ww/en/view/109763408>)\n\n**\\--------- Begin Update C Part 2 of 2 ---------**\n\n * SIMATIC Field PG M5: Update BIOS to [v22.01.08](<https://support.industry.siemens.com/cs/ww/en/view/109763408>)\n * SIMATIC Field PG M6: Update BIOS to [v26.01.07](<https://support.industry.siemens.com/cs/ww/en/view/109763408>)\n\n**\\--------- End Update C Part 2 of 2 ---------**\n\nSiemens is preparing further updates and recommends the following specific workarounds and mitigations users can apply to reduce the risk until fixes are available.\n\n * As a prerequisite for an attack, an attacker must be able to run untrusted code on affected systems. Siemens recommends limiting the possibilities to run untrusted code if possible.\n * Applying a defense-in-depth concept can help to reduce the probability that untrusted code is run on the system. Siemens recommends applying the [defense-in-depth concept](<https://www.siemens.com/industrialsecurity>).\n\nAs a general security measure, Siemens strongly recommends protecting network access to devices with appropriate mechanisms. In order to operate the devices in a protected IT environment, Siemens recommends configuring the environment according to [Siemens\u2019 operational guidelines for Industrial Security](<https://www.siemens.com/cert/operational-guidelines-industrial-security>), and following the recommendations in the product manuals.\n\nAdditional information on Industrial Security by Siemens can be found at: <https://www.siemens.com/Industrialsecurity>\n\nFor more information on these vulnerabilities and the associated mitigations, please see Siemens security advisory [SSA-534763](<https://new.siemens.com/global/en/products/services/cert.html#SecurityPublications>)\n\nCISA recommends users take defensive measures to minimize the risk of exploitation of this vulnerability. CISA reminds organizations to perform proper impact analysis and risk assessment prior to deploying defensive measures. \n \nCISA also provides a section for [control systems security recommended practices](<https://us-cert.cisa.gov/ics/recommended-practices>) on the ICS webpage on [us-cert.cisa.gov](<https://us-cert.cisa.gov/ics>). Several recommended practices are available for reading and download, including [Improving Industrial Control Systems Cybersecurity with Defense-in-Depth Strategies](<https://us-cert.cisa.gov/sites/default/files/recommended_practices/NCCIC_ICS-CERT_Defense_in_Depth_2016_S508C.pdf>).\n\nAdditional mitigation guidance and recommended practices are publicly available on the [ICS webpage on us-cert.cisa.gov](<https://us-cert.cisa.gov/ics>) in the Technical Information Paper, [ICS-TIP-12-146-01B--Targeted Cyber Intrusion Detection and Mitigation Strategies](<https://us-cert.cisa.gov/ics/tips/ICS-TIP-12-146-01B>). \n \nOrganizations observing any suspected malicious activity should follow their established internal procedures and report their findings to CISA for tracking and correlation against other incidents.\n\nNo known public exploits specifically target this vulnerability. This vulnerability is not exploitable remotely.\n\n## \nContact Information\n\nFor any questions related to this report, please contact the CISA at: \n \nEmail: [CISAservicedesk@cisa.dhs.gov](<mailto:cisaservicedesk@cisa.dhs.gov>) \nToll Free: 1-888-282-0870\n\nFor industrial control systems cybersecurity information: https://us-cert.cisa.gov/ics \nor incident reporting: https://us-cert.cisa.gov/report\n\nCISA continuously strives to improve its products and services. You can help by choosing one of the links below to provide feedback about this product.\n\nThis product is provided subject to this Notification and this [Privacy & Use](<https://www.dhs.gov/privacy-policy>) policy.\n\n**Please share your thoughts.**\n\nWe recently updated our anonymous [product survey](<https://www.surveymonkey.com/r/CISA-cyber-survey?product=https://us-cert.cisa.gov/ics/advisories/icsa-20-252-07>); we'd welcome your feedback.\n", "edition": 9, "modified": "2021-02-09T00:00:00", "published": "2021-02-09T00:00:00", "id": "ICSA-20-252-07", "href": "https://www.us-cert.gov//ics/advisories/icsa-20-252-07", "title": "Siemens Industrial Products (Update C)", "type": "ics", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}], "virtuozzo": [{"lastseen": "2020-06-25T12:41:08", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "This update provides a new kernel 2.6.32-042stab145.3 for Virtuozzo Containers for Linux 4.7 and Server Bare Metal 5.0. It is based on the RHEL 6.10 kernel 2.6.32-754.30.2.el6 and inherits security and stability fixes from it. The new kernel also provides internal stability fixes.\n**Vulnerability id:** CVE-2020-0543\nhw: Special Register Buffer Data Sampling (SRBDS).\n\n", "edition": 2, "modified": "2020-06-22T00:00:00", "published": "2020-06-22T00:00:00", "id": "VZA-2020-044", "href": "https://help.virtuozzo.com/s/article/VZA-2020-044", "title": "Important kernel security update: New kernel 2.6.32-042stab145.3 for Virtuozzo Containers for Linux 4.7, Server Bare Metal 5.0", "type": "virtuozzo", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}, {"lastseen": "2020-06-25T12:41:44", "bulletinFamily": "unix", "cvelist": ["CVE-2020-0543"], "description": "This update provides a new kernel 2.6.32-042stab145.3 for Virtuozzo 6.0. It is based on the RHEL 6.10 kernel 2.6.32-754.30.2.el6 and inherits security and stability fixes from it. The new kernel also provides internal stability fixes.\n**Vulnerability id:** CVE-2020-0543\nhw: Special Register Buffer Data Sampling (SRBDS).\n\n", "edition": 2, "modified": "2020-06-22T00:00:00", "published": "2020-06-22T00:00:00", "id": "VZA-2020-045", "href": "https://help.virtuozzo.com/s/article/VZA-2020-045", "title": "Important kernel security update: New kernel 2.6.32-042stab145.3; Virtuozzo 6.0 Update 12 Hotfix 52 (6.0.12-3759)", "type": "virtuozzo", "cvss": {"score": 2.1, "vector": "AV:L/AC:L/Au:N/C:P/I:N/A:N"}}]}