Lucene search
+L

riscv: save the SR_SUM status over switches

🗓️ 04 Sep 2025 00:02:03Reported by MicrosoftType 
mscve
 mscve
🔗 msrc.microsoft.com👁 4 Views

RISC-V: save the supervisor status across context switches.

Related
ReporterTitlePublishedViews
Family
bdu_fstec
The vulnerability of the riscv component in the Linux operating system’s kernel allows a hacker to trigger a service failure.
28 Oct 202500:00
bdu_fstec
cgr
CVE-2025-38261 vulnerabilities
2 Feb 202613:17
cgr
circl
CVE-2025-38261
9 Jul 202511:01
circl
cnnvd
Linux kernel 安全漏洞
9 Jul 202500:00
cnnvd
cve
CVE-2025-38261
9 Jul 202510:42
cve
cvelist
CVE-2025-38261 riscv: save the SR_SUM status over switches
9 Jul 202510:42
cvelist
debiancve
CVE-2025-38261
9 Jul 202510:42
debiancve
euvd
EUVD-2025-20800
3 Oct 202520:07
euvd
nvd
CVE-2025-38261
9 Jul 202511:15
nvd
openvas
Ubuntu: Security Advisory (USN-7833-1)
23 Oct 202500:00
openvas
Rows per page

Data

Build on a solid foundation with Vulners data

We provide the essential building blocks for cybersecurity solutions with comprehensive, structured, and constantly updated vulnerability and exploits data

Api

Power your application with Vulners API

The Vulners REST API offers reliable, high-performance access to vulnerability intelligence, with 99.9% SLA uptime and CDN-backed data delivery for seamless global access

App

Assess and manage vulnerabilities with Vulners tools

Built on top of Vulners' database and SDK, end-user solutions give security professionals and developers lightweight and powerful tools for vulnerability remediation

25 Nov 2025 01:39Current
7High risk
Vulners AI Score7
CVSS 3.15.5
EPSS0.00132
4