In the Linux kernel, the following vulnerability has been resolved: spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.
OS | Version | Architecture | Package | Version | Filename |
---|---|---|---|---|---|
Debian | 12 | all | linux | <= 6.1.106-3 | linux_6.1.106-3_all.deb |
Debian | 11 | all | linux | < 5.10.223-1 | linux_5.10.223-1_all.deb |
Debian | 999 | all | linux | < 6.10.3-1 | linux_6.10.3-1_all.deb |
Debian | 13 | all | linux | < 6.10.3-1 | linux_6.10.3-1_all.deb |