L3 CPU shared cache architecture is susceptible to a Flush+Reload side-channel attack

2013-10-01T00:00:00
ID VU:976534
Type cert
Reporter CERT
Modified 2013-11-01T00:00:00

Description

Overview

L3 CPU shared cache architecture is susceptible to a Flush+Reload side-channel attack, resulting in information leakage. allowing a local attacker to derive the contents of memory not belonging to the attacker.

Description

Common L3 CPU shared cache architecture is susceptible to a Flush+Reload side-channel attack, as described in "Flush+Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack" by Yarom and Falkner.

By manipulating memory stored in the L3 cache by a target process and observing timing differences between requests for cached and non-cached memory, an attacker can derive specific information about the target process. The paper demonstrates an attack against GnuPG on an Intel Ivy Bridge platform that recovers over 98% of the bits of an RSA private key.

This vulnerability is an example of CWE-200: Information Exposure.


Impact

A local attacker can derive the contents of memory shared with another process on the same L3 cache (same physical CPU). Virtualization and cryptographic software are examples that are likely to be vulnerable.

An attacker on the same host operating system only needs read access to the executable file or a shared library component of the target process.

An attacker on a different virtual machine similarly needs access to an exact copy of the executable or shared library used by the target process, and the hypervisor needs to have memory page de-duplication enabled.


Solution

Apply an Update
See the Vendor Information section below for additional information.

GnuPG has released GnuPG version 1.4.14 and Libgcrypt 1.5.3 to to address this vulnerability. CVE-2013-4242 has been assigned to the specific GnuPG vulnerability described in the Yarom/Falkner paper. The CVSS score below applies specifically to CVE-2013-4242.


Disable Memory Page De-duplication

To prevent this attack on virtualization platforms, disable hypervisor memory page de-duplication.


Vendor Information

Any shared cache architecture may be susceptible to side-channel or timing attacks. CPU vendors are listed as "Not Affected" since the cache architecture is functioning as designed. It is generally up to an operating system or application to take appropriate measures to protect sensitive information.


Vendor| Status| Date Notified| Date Updated
---|---|---|---
libgcrypt| | 16 Aug 2013| 16 Aug 2013
Linux KVM| | 15 Aug 2013| 16 Aug 2013
Red Hat, Inc.| | 13 Sep 2013| 13 Sep 2013
VMware| | 16 Aug 2013| 03 Sep 2013
Xen| | 16 Aug 2013| 03 Sep 2013
AMD| | 16 Aug 2013| 29 Oct 2013
Cryptlib| | 16 Aug 2013| 03 Sep 2013
GnuTLS| | 16 Aug 2013| 03 Sep 2013
Intel Corporation| | 16 Aug 2013| 03 Sep 2013
OpenSSL| | 16 Aug 2013| 03 Sep 2013
Amazon| | 16 Aug 2013| 03 Sep 2013
Attachmate| | 16 Aug 2013| 03 Sep 2013
Certicom| | 16 Aug 2013| 16 Aug 2013
Crypto++ Library| | 16 Aug 2013| 16 Aug 2013
EMC Corporation| | 16 Aug 2013| 16 Aug 2013
If you are a vendor and your product is affected, let us know.

CVSS Metrics

Group | Score | Vector
---|---|---
Base | 2.4 | AV:L/AC:H/Au:S/C:P/I:P/A:N
Temporal | 1.9 | E:POC/RL:OF/RC:C
Environmental | 2.3 | CDP:ND/TD:M/CR:H/IR:H/AR:ND

References

  • <http://eprint.iacr.org/2013/448.pdf>
  • <http://cwe.mitre.org/data/definitions/200.html>
  • <http://lists.gnupg.org/pipermail/gnupg-announce/2013q3/000330.html>
  • <http://lists.gnupg.org/pipermail/gnupg-announce/2013q3/000329.html>

Credit

Thanks to Yuval Yarom and Katrina Falkner for reporting this vulnerability and for help writing this document.

This document was written by Adam Rauf.

Other Information

  • CVE IDs: CVE-2013-4242
  • Date Public: 05 Sep 2013
  • Date First Published: 01 Oct 2013
  • Date Last Updated: 01 Nov 2013
  • Document Revision: 39